set_dont_touch in synthesis

[xworld2008]

set_dont_touch

when i finish elaborate step using dc, i get GTECH netlist. i set dont_touch in this module, and then synthesize this module or synthesize the upper module, i want to know that whether i can get the gatelist that have mapped to target library?

 

[wkong_zhu]

synopsys set_dont_touch

I think you can't

 

[eda_wiz]

set dont touch synopsys dc

when i finish elaborate step using dc, i get GTECH netlist. i set dont_touch in this module, and then synthesize this module or synthesize the upper module, i want to know that whether i can get the gatelist that have mapped to target library?

If the module to which you applied constraint dont_touch is a library specific cell instatiated module.. it will be fine...(means that module is already a netlist for target libary) ,otherwise the GTECH netlist wont be mapped into target library...

regards

 

[xworld2008]

set_dont_touch synopsys

BUT i find that the GTECH cell that no instantiated to target library cell had not mapped to target library.i get the gate netlist including GTECH cell.

 

[eda_wiz]

set_dont_touch dc_shell

Hi xworld2008,
thats what i said... if ur code is in RTL form..and u apply dont_touch.. netlist will be GTECH format..

if u have library specific instantiated cells.. move that part of the code to a seperate module and apply dont_touch on it..

 

[wkong_zhu]

set_dont_touch in dc

Synopsys will do nothing to don't-touch designs

 

[ram]

synopsys design compiler set_dont_touch

you may not get it if you are using dont touch

 

[haosg]

set_dont_touch current_design

right, for some simple logic, you need direct instanciate library cell in RTL, and set dont_touch before compile.
e.g, clock gating cell, or clock muxplixer.

 

[optor]

synopsys dont touch

I think DC will not compile and optimize this set_dont_touch module.

 

[kctang]

synthesis using gtech

If you want to retain the module don't touch in top level synthesis, you can do the following:

1. set current design to that sub-module.
2. Do synthesis on this module.
3. Set don't touch attribute on this module or set current design to top module and apply don't touch on that instance.
4. Do top level synthesis.

 

[subraml]

set_dont_touch on cell

hi u can do like this
u can easily convert the gtech components into ur desired library components

just in DC compiler make target library( which library ur using now )
and read the file which have gtech componets and do the follwing steps
this will give the design with ur liberary componente

then using that file u can do ur synthesis

the steps to convert the gtech componenets
1. make the traget library
2. read_file -
3. current_design module name
4.link
5. give the translate command
6. write file in verilog format
after this u can use this file

Pls find the related details in translate comment in DC tools directory

 

[xwcwc1234]

gtech library ,netlist

Hi all,
I want a DC script file for whole chip synthesis. Anyone knows where to get such a file ?

 

[spauls]

set_dont_touch synthesis pragma in rtl

search www.synopsys.com , there is one script in Solvnet

 

[bravobravo]

how to set dont touch on cells in rtl

search www.synopsys.com , there is one script in Solvnet

Dear sir :
can you help us .. .about it , if you really know the link of it or you have got it in you hand..
becos .. solvenet .. need password ...anyway ...