Feb 12, 2009 #1 K kingmaker Junior Member level 2 Joined Apr 3, 2008 Messages 22 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,429 Im asked to use mentor graphic to design serial-to-parallel shift register. Anyone got idea for this design?
Im asked to use mentor graphic to design serial-to-parallel shift register. Anyone got idea for this design?
Feb 12, 2009 #2 D Digital-L0gik Member level 2 Joined Jan 26, 2009 Messages 44 Helped 5 Reputation 10 Reaction score 4 Trophy points 1,288 Activity points 1,577 Try posting your own ideas first and we can guide you along. This way we wont have to spoon feed you. **broken link removed**
Try posting your own ideas first and we can guide you along. This way we wont have to spoon feed you. **broken link removed**
Feb 18, 2009 #3 F fpga_asic_designer Junior Member level 3 Joined Nov 4, 2007 Messages 30 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,286 Activity points 1,478 that doesn't sound too hard. you can simply code it up using verilog always @ (posedge iclk) begin q[5] <= q[4]; q[4] <= q[3]; q[3] <= q[2]; q[2] <= q[1]; q[1] <= q[0]; q[0] <= id; if (cnt == 'h5) cnt <= 'h0; else cnt <= cnt + 1; end always @ (posedge iclk) begin if (cnt == 'h5) odata <= q[5:0]; else odata <= odata; end
that doesn't sound too hard. you can simply code it up using verilog always @ (posedge iclk) begin q[5] <= q[4]; q[4] <= q[3]; q[3] <= q[2]; q[2] <= q[1]; q[1] <= q[0]; q[0] <= id; if (cnt == 'h5) cnt <= 'h0; else cnt <= cnt + 1; end always @ (posedge iclk) begin if (cnt == 'h5) odata <= q[5:0]; else odata <= odata; end