serial to parallel converter using state machine

[Junus2012]

Dear friends

I writing a code for serial to parallel converter, the serial data consist of 10 bits, (start bit, 7 data bits, parity bit, end bit).. the conversion starts when the start bit is one and ended with end bit.

I used the state machine for reading the data in sequence and at the end put all them together in a register and show them at the output.

The problem I getting is that my state machine stop at state seven (which is related to data seven of the input), after that the state machine goes to the first state which i named it idle and ignores the state eight, nine.

if you look on to my code you will see im clearly put the condition to go state eight after seven or nine after eight,, but I cant find any reason that makes those states doesnt appear.

Please I need your kind help and any suggestion will be very appreciated.
thank you very much;


below is my code

*********************************************

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Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
 
 
entity spc_state is
    Port ( clk : in  STD_LOGIC;
           rst : in  STD_LOGIC;
           d_in : in  STD_LOGIC;
           ready : out  STD_LOGIC:='0';
           err : out  STD_LOGIC:='0';
           d_out : out  STD_LOGIC_VECTOR (6 downto 0):="0000000");
end spc_state;
 
architecture Behavioral of spc_state is
 
type state is (idle, one, two, three, four, five, six, seven, eight, nine);
signal pres_state, next_state : state;
signal reg : std_logic_vector (9 downto 1);
 
begin
 
process (clk, rst)
begin
 
if (rst = '1')then
pres_state <= idle;
 
elsif (clk' event and clk = '1') then
pres_state <= next_state;
 
end if;
end process; 
 
process (pres_state, d_in)
begin
 
next_state <= pres_state;
 
case pres_state is 
 
when idle => if d_in = '1' then 
                next_state <= one;
                 else next_state <= idle;
                 end if;
                 
when one => reg(1)<= d_in;
            next_state <= two;
                
when two => reg(2)<= d_in;
            next_state <= three;
                
when three => reg(3)<= d_in;
            next_state <= four;
                
when four => reg(4)<= d_in;
            next_state <= five;
                
when five => reg(5)<= d_in;
            next_state <= six;
                
when six => reg(6)<= d_in;
            next_state <= seven;
                
when seven => reg(7) <= d_in;
            next_state <= eight;
                
when eight => reg(8) <= d_in;
             next_state <= nine;
                 
when nine => reg(9) <= d_in;
             next_state <= idle;
 
when others => next_state <= idle;
 
end case;
end process;
 
process (pres_state)
 
variable temp : std_logic:='0';
variable temp2: std_logic_vector(7 downto 1):="0000000";
begin
 
 
case pres_state is 
 
when idle => temp := reg(1) xor reg(2) xor reg(3) xor reg(4) xor reg(5) xor reg(6) xor reg(7) xor reg(8) xor reg(9);
             err <= temp;
             if temp = '0' then 
                    ready <= '1';
             d_out <= reg(7 downto 1);
                 temp2 := reg(7 downto 1);
                 end if;
 
when others => d_out <= temp2;
 
end case;
 
end process;
 
 
end Behavioral;

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[FvM]

The problem I getting is that my state machine stop at state seven (which is related to data seven of the input), after that the state machine goes to the first state which i named it idle and ignores the state eight, nine.

I can't confirm the observation. The present code goes through all nine states after a '1' data input.

If the code is intended as an UART design, it's missing a number of things.

 

[Analog Ground]

The "rst" input can send the state machine back to idle at any time if it is active. (If the rst code is correct). Anything going on with rst?

 

[Junus2012]

Dear Fvm

nice to see you again, its been long time

First thank you for your response

logically, there is no obvious or clear reason so the machine doesnt go to the eight or nine state,,, I got another confermation of the mistake,,, in the reset I have assigned the state to nine, but again it doesnt show nine, directly show idle rather..

As you said, im trying to use code in UART, kindly could you tell me please what is missing,, if you have some material about it with vhdl then plz it also help

many thanx

I can't confirm the observation. The present code goes through all nine states after a '1' data input.

If the code is intended as an UART design, it's missing a number of things.

- - - Updated - - -

The "rst" input can send the state machine back to idle at any time if it is active. (If the rst code is correct). Anything going on with rst?

hii

no no, the rst is not working well if i assign it to states from one to seven but eight and nine doesnt work with rst

 

[aruipksni]

Dear Fvm

nice to see you again, its been long time

First thank you for your response

logically, there is no obvious or clear reason so the machine doesnt go to the eight or nine state,,, I got another confermation of the mistake,,, in the reset I have assigned the state to nine, but again it doesnt show nine, directly show idle rather..

As you said, im trying to use code in UART, kindly could you tell me please what is missing,, if you have some material about it with vhdl then plz it also help

many thanx





- - - Updated - - -



hii

no no, the rst is not working well if i assign it to states from one to seven but eight and nine doesnt work with rst

sorry for the dumb question, but how do you know what states are taken ?
are you doing some simulation or using chipscope or logic analyser ?
mabee it actually works ...

 

[Junus2012]

sorry for the dumb question, but how do you know what states are taken ?
are you doing some simulation or using chipscope or logic analyser ?
mabee it actually works ...

im checking it by simulation

your suggestion is not dump, because sometimes i see some of my design work practically but not by simulation,, hope this will be the same case

 

[FvM]

I believe that you simulated a different code than that in post #1, because I don't see the said problem.

For a full operational UART design you need a baud rate generator, oversampling of input data, check for valid start bit after a half bit period.

 

[aruipksni]

im checking it by simulation

your suggestion is not dump, because sometimes i see some of my design work practically but not by simulation,, hope this will be the same case

mabe your simulation time resolution is too low ?

if you have modelsim you need to :
vsim -t ps