Serial lvds adc ads5263

[mehran1367]

hi
i have problem. ads5263 is serial ADC. can anyone help me?
my sampling is not good.

 

[ads-ee]

What is your question? What do you mean your sampling is not good? Where is the proof that this is the case? Where is the data, the waveforms, the scope traces, the captures from chipscope/signaltap, etc, and why you think your data is sampled incorrectly?

 

[FvM]

The fact that you posted in the PLD section suggests that you are connecting the device to a FPGA. That's the point where your detailed problem report may start.

 

[mehran1367]

What is your question? What do you mean your sampling is not good? Where is the proof that this is the case? Where is the data, the waveforms, the scope traces, the captures from chipscope/signaltap, etc, and why you think your data is sampled incorrectly?

i designed a daughter board. it has an fmc connector, cdce62005 and ads5263. i have several problems. i listed my problems. before that i want to give a summary about what i did.
summary: i used a single 10 mhz clock as an input for cdce62005. cdce62005 programed to pass this signal to its lvds output buffer. so a 10mhz lvds signal is an input clock for ads5263. ads5263 has different sampling modes. i used 2 of this modes. one is 16bit serialization word format with one channel. second one is 16bit serialization word format with two channels. ads5263 gives two clocks for sampling. one is lclk(bit clock) and the second is adclk(frame clock). these two clocks have different phase modes. i use one which is showed in pic below. in this mode we have 4 rising edge of lclk while adclk is "1" and we have 4 rising edge of lclk while adclk is "0".

**broken link removed**

in the first mode i used a 400khz signal as an input to channel one of ads5263.lclk 1s 80mhz and adclk is 10mhz. i saw glitches so i decided to check ramp mode of this ic as a test to verify my code. i saw something strange in chipscope waves. i saw that lclk and adclk are ok . but some where in waves i saw that we have 3 rising edge of lclk while adclk is "0". instead of 4. and some where we have 5 rising edge. i dont know why ???? can i fix this?. i just used obufds for these 2 clocks. and a dcm for lclk.

in first mode when i used a clock more than 25 mhz i dont see any clock ( lclk and adclk) in spectrum.

in second mode adclk is 5 mhz and lclk is 40 mhz for 10mhz input clock. when i used a clock more than 45 mhz i dont see any clock ( lclk and adclk) in spectrum.

please help me

i think i have two different problems. should we think about them seperately?

 

[FvM]

According to datasheet, 10 MHz input clock (resulting in 10 MHz sample rate) is the minimal operation frequency. 5 MHz isn't guaranteed to work.

I don't know what's the purpose of cdce62005, but presumed it outputs a clean, continuous clock, it shouldn't hurt.

All other points are referring to hardware and FPGA design questions.

Firstly the ADC needs good circuit layout and power supply bypassing to achieve reasonable performance, worst case even the internal PLL clock generation might fail.

Secondly the bit and frame clock connection from the ADC to the FPGA must be correctly differential routed with required termination and correctly selected IO standard on the FPGA side. Presumed you are using an eval board designed for differential IO standards, this should be no problem on this side.

Finally there may be problems in the SERDES implementation.

Regarding "missing" bitclock edges, you understand that you need a respective Chipscope oversampling rate (e.g. 4xbit clock frequency) not to miss a pulse? Must be an additionally PLL generated clock, should be possible with the presently used 10 MHz ADC sampling rate.

There's a certain risk that the ADC does not work correctly at the lower sampling rate limit, but less likely.

 

[mehran1367]

According to datasheet, 10 MHz input clock (resulting in 10 MHz sample rate) is the minimal operation frequency. 5 MHz isn't guaranteed to work.

I don't know what's the purpose of cdce62005, but presumed it outputs a clean, continuous clock, it shouldn't hurt.

All other points are referring to hardware and FPGA design questions.

Firstly the ADC needs good circuit layout and power supply bypassing to achieve reasonable performance, worst case even the internal PLL clock generation might fail.

Secondly the bit and frame clock connection from the ADC to the FPGA must be correctly differential routed with required termination and correctly selected IO standard on the FPGA side. Presumed you are using an eval board designed for differential IO standards, this should be no problem on this side.

Finally there may be problems in the SERDES implementation.

Regarding "missing" bitclock edges, you understand that you need a respective Chipscope oversampling rate (e.g. 4xbit clock frequency) not to miss a pulse? Must be an additionally PLL generated clock, should be possible with the presently used 10 MHz ADC sampling rate.

There's a certain risk that the ADC does not work correctly at the lower sampling rate limit, but less likely.

so whats your idea about the higher frequency that i can not see any clock(lclk or ADclk)in spectrum?

- - - Updated - - -

i used a 240 mhz clock from dcm as chipscope clock. but the dcm input a 100mhz clock from mother board

 

[ads-ee]

So do you have any chipscope captures (using the 240 MHz chipscope clock) showing the problem of 3/4/5 lclk while adclk is low?

 

[mehran1367]

i have .prn file. can i open this with chipscope again?

 

[mehran1367]

any help about serial ADC?

 

[ads-ee]

any help about serial ADC?

Still need information and captures of the waveforms. Can't effectively help with guessing about what you're seeing.

 

[mehran1367]

HI, Finally i prepared the images



Can any body help me?

 

[FvM]

What's the ADC input clock and chipscope sampling frequency in this acquisition? You previously reported 240 MHz chipscope frequency which would correspond to 7.5 MHz ADC clock. But minimum ADC clock frequency is 10 MHz, see post #5.

In any case the waveform suggests unlocking of the ADC PLL, may be caused either by unsuitable clock frequency, bad clock signal quality, power supply noise or insufficient ADC chip bypassing. It would be interesting to see the ADC input clock in the chipcope waveform.

 

[mrflibble]

You could probe the LCLK or ADCCLK signal to see if you actually get a stable clock there. Seeing your clock signal on an oscilloscope tends to generate "ah hah" moments every now and then. Or if that's not an option for whatever reason you can sample those same signals in chipscope as already suggested.

 

[mehran1367]

well, my clock frequency is 10 mhz. and chip scope clock is 320mhz.
i used a dcm which its input is lclk and output 4xlclk=320mhz

i think its true. pll is not locked. but what the reason?

input clock?

tanx

 

[FvM]

The settings seem to be O.K. Some possible causes for PLL unlock have been mentioned previously, but I fear there's litte chance to diagnose the problem from a distance.

 

[ads-ee]

Okay I'll try one last time to see if you will provide useful information to help you.

1. Provide all code that interfaces to the ADS5263.
2. provide the testbench of that code (if there is a testbench)
3. provide the setting used for ADS5263 registers (if not readily apparent from the code in 1)
4. Use the datasheet and tell me which figure your output is supposed to be using (Fig 69 - Fig 74)
5. Explain which LCLK phase you are using (Fig 75 & 76)

Also are you sure you programmed both the CDCE62005 and the ADS5263 correctly for an LVDS clock source. Perhaps the reason the PLL in the ADS5263 doesn't lock properly is because they aren't using the same signaling standard.