SERDES termination methods

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Hello all,

I have a question about the SERDES terminations methods. In the DDR world, we have different termination specs for LPDDR, DDR3(SSTL), DDR4/5(POD).
Is this the same story in SERDES world? Are PCIe, SATA,XAUI, etc having different terminations? Where can i find the summary of those termination methods?

Thank you!
 

Why not review the respective standards? In a short, they are all using 100 ohm differential termination.
 

FvM said:
Why not review the respective standards? In a short, they are all using 100 ohm differential termination.
Click to expand...

Hello FvM,

Yes. I wanted to do that. However I'm not familiar with SERDES standard organizations and document. I know I can get DDR4/5 standards from JEDEC website.
How do I find SERDES standards? If you can point me one, that will be very helpful.

Thank you!
 

Hi,

A simple internet search will do.
Or wikipedia...
Or a search for application notes on any SERDES IC manufacturer..
Or...

Klaus
 

If you are looking for the standard. SERDES uses CML or Current Mode Logic. The term SERDES describes the upper layer protocol for the Serilaizer and Deserializer.

You can have SERDES that uses some other differential standard like LVDS, but the majority of high speed mulit-Gb type interfaces use CML.
 

Hi,

It seems the termination method changes based on the protocols.
Click to expand...
Never heard that termination depends on protocol. In my eyes this makes no sense.
I've just tried to find this information in the given document. Which page are you referring to?

Klaus
 


I noticed some products have a option to have external or internal capacitive coupling. Is it because of the bandwidth limit?
 

Hi,

Often capacitive coupling is used to suppress DC current ... useful if you want to drive an isolating transformer.

Klaus
 

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