Sequential Adder at RTL level

[kotak86]

Hi I am trying to implement code for 4 bit sequential adder at RTL level. I newbie in verilog programming.

My approach is as below:

Design 1 bit full adder - combinational
Design 4 bit full adder - combinational -- instantiate 1 bit 4 times

Then I have dump(please see code below) my input and output to the reg @ posedge clk......


but I am not getting expecting output...............

I am not allow to use a+b kinds of equation as well not have to use gate in my design as I have to synthesized this design in Toshiba library

module rca_4(sum_rg, cout_rg, a, b, c_in, clk);
  
  input [3:0]a, b; 
  input c_in, clk;
  output reg [3:0]sum_rg; 
  output reg cout_rg;
  reg [3:0]a_rg, b_rg;
  reg cin_rg ;
  wire w1, w2, w3, c_out;
  wire [3:0]sum;
  
  rca_4c MA (sum, c_out, a_rg, b_rg, c_in_rg);
  
  
always @ (posedge clk)

begin 
    a_rg <= a;
    b_rg <= b;
  cin_rg <= c_in;
  sum_rg <= sum;
 cout_rg <= c_out;
    
end
  

endmodule 


module rca_1 (sum, c_out, a, b, c_in);
  input a, b, c_in;
  output sum, c_out;
  
   
 assign   sum = (a ^ b ^ c_in);
 assign c_out =((a & b ) | (b & c_in) | (a & c_in)) ;

endmodule


module rca_4c (sum, c_out, a, b, c_in);
  input [3:0] a, b;
  input c_in;
  output [3:0]sum;
  output c_out;
  wire c1, c2, c3;
  
  rca_1 M1 (sum[0], c1, a[0], b[0], c_in);
  rca_1 M2 (sum[1], c2, a[1], b[1], c1);
  rca_1 M3 (sum[2], c3, a[2], b[2], c2);
  rca_1 M4 (sum[3], c_out, a[3], b[3], c3);
  
endmodule

Thanks
Ankit

 

[alah]

SORRY, Ankit. At LEAST I answered, just to say DONT give up.
Some Day, Some Where, Some Body will HELP, I EXPECT.

 

[kotak86]

Sorry but I did not get you

 

[alah]

Hi Ankit; I dont know much about programming and less about verilog. I only browsed the UNANSWERED psts to see if I could help.
I can help with discrete LOGIICJust hope you solved your problem, if not google it. what about your school friends?
GOOD LUCK, just DONT give up.

 

[vimalraj205]

hai ankit,

you said its combinational circuit and then y you declare clk in the first line of your coding
in that clk does not match any argument in the whole programing try that without the clk declarartion

 

[permute]

anyways, you have cin_rg and c_in_rg

verilog will create a 1b wire if you have a typo. In some rare cases this will actually be valid.

You really should encourage and use:
'default_nettype none

though this sadly can affect anyone lame enough to have intentionally used an implicitly declared 1b wire.