As per your program, you will only get the following condition passed..
if (i == 2'b00)
begin
gen_data_reg_1_0 <= 16'h2000;
gen_data_reg_3_2 <= 16'hb505;
gen_data_reg_5_4 <= 16'h0000;
gen_data_reg_7_6 <= 16'h0201;
end
I dont know how you are getting the passed conditions for 2b01 and 2b10...
If simulation is OK, then I expect the reality is OK, too.
Bus type: Now I´m about sure that it is called a 64 bit wide parallel bus with SDR (single data rate)
What is your serial clock?
Maybe it´s a transmission line problem or a receiver problem - in real world.
How did you do the real world testing?
If you want serial you normally shift out of your parallel register.
Look at parallel in serial out (PISO)
From what I've read you are correctly assigning parallel data to your registers based on your I select. (You could also use a case statement here.)
On a side note in your simulation the value of I says it's a 32 bit register. This is common of integers.
I also see the you are getting values expected for i == 2'b11, however this is all happening a clock cycle after the conditional statement.