Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

selection of clock duty cycle

Status
Not open for further replies.

madmax

Newbie level 6
Joined
Jan 10, 2003
Messages
12
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
120
abel 25% duty cycle clock

Hi ,

I have to transfer a data from Flip flop1 to Flip flop2,Flip flop's hold time is '0' and clk to q delay is 'x' ns.Between Flip flops there are combinational logics which takes 'y' ns.I'm having a pulse whose high period is more than 'x' ns.Its duty cyle is 20% high and 80% low.Can I use this pulse or is there any need that I have to use a clock having dutycycle of 30% or 40% or 50% high and 70% or 60% or 50 % low.Assume both the frequency of the clock and pulse are same.Is there any notes which says about the duty cycles selection of a clock.

Thanks in advance ,

Max
 

elektrom

Full Member level 2
Joined
Jul 2, 2001
Messages
127
Helped
3
Reputation
6
Reaction score
1
Trophy points
1,298
Activity points
965
duty cycle

I don't understand your design (MHz?, Buit-in ram?, FPGA?, ASIC?) but, basically, If all of flip flop is clocking with the same edge (rising-edge/falling-edge), No need to worry about duty cycle. In my opinion, duty cycle should be around 25~75%. 20% may not good enough.
 

Pim

Member level 3
Joined
Jan 26, 2002
Messages
57
Helped
2
Reputation
4
Reaction score
2
Trophy points
1,288
Activity points
1,027
Re: duty cycle

Not having seen your design, nor fully understanding your description of it I can not give you a perfect advise. However, in general the question of duty cycle is not the main issue, but the time that signals must be held stable on the flip-flop's inputs prior to the triggering signal (the clock signal). Also, you must not forget to check out what the worst-case times are. In addition, do not forget that flip-flop's are sometimes sensitive to dips and spikes on the power supply as well as interference (in case you for example wire-wrap the design and use CMOS and long wires for the input signals -> will be capacitively and inductively coupled to nearby wires and having high input impedance of the CMOS inputs means caution).

/Pim

madmax said:
Hi ,

I have to transfer a data from Flip flop1 to Flip flop2,Flip flop's hold time is '0' and clk to q delay is 'x' ns.Between Flip flops there are combinational logics which takes 'y' ns.I'm having a pulse whose high period is more than 'x' ns.Its duty cyle is 20% high and 80% low.Can I use this pulse or is there any need that I have to use a clock having dutycycle of 30% or 40% or 50% high and 70% or 60% or 50 % low.Assume both the frequency of the clock and pulse are same.Is there any notes which says about the duty cycles selection of a clock.

Thanks in advance ,

Max
 

madmax

Newbie level 6
Joined
Jan 10, 2003
Messages
12
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
120
Hi ,

If my flip flop is able to produce the output within the pulse period then can i use a pulse instead of a clock ,if all my flip flops are working in rising edge.

thanx in advance ,

max
 

jiang

Advanced Member level 4
Joined
Dec 31, 1999
Messages
111
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,296
Location
Taiwan
Activity points
855
madmax said:
Hi ,

If my flip flop is able to produce the output within the pulse period then can i use a pulse instead of a clock ,if all my flip flops are working in rising edge.

thanx in advance ,

max
is your design in physical phase? do you have experience with clock tree layout?
if not, using gating clock in your design is a worst choice.
using gating clock, you must take care more in physical design.
 

madmax

Newbie level 6
Joined
Jan 10, 2003
Messages
12
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
120
Thank you jiang

I'm using FPGA so I think no need to care about physical layout.So for FPGA can I use a pulse mentioned having the above mentioned conditions.
 

FNK

Member level 3
Joined
Jan 25, 2003
Messages
67
Helped
5
Reputation
10
Reaction score
5
Trophy points
1,288
Activity points
470
I think the best way to verify is to do timing simulation with your defined clock. This way it will get clear if it will work or not.
 

elektrom

Full Member level 2
Joined
Jul 2, 2001
Messages
127
Helped
3
Reputation
6
Reaction score
1
Trophy points
1,298
Activity points
965
duty cycle

madmax said:
Hi ,

If my flip flop is able to produce the output within the pulse period then can i use a pulse instead of a clock ,if all my flip flops are working in rising edge.

thanx in advance ,

max
The answer is possible. But!!. Try to feed this output to global clock buffer in FPGA and use its output signal as a global clock for all flip flops.
Without global clock buffer, It's easy to face with clock skew problem.

PS. You may have to instanciate a global clock buffer by hand.
 

Status
Not open for further replies.
Toggle Sidebar

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top