Maintaining proper shape of clock

[fragnen]

We put clock buffers to propagate clocks inside a SOC.
Now that same clock that propagates inside the SOC needs to be connected as a output from a SOC to a clock input if another block named blk_a as a clock to blk_a. How can the shape of this clock be maintained outside the SOC as we cannot use clock buffers when the clock propagates from output of SOC to input of blk_a?

 

[Qwerty112233]

You might only be able to provide the clock at your soc output port with an agreed upon transition, pulse width, period..after that someone should be owning the level that sees this SOC to blkA clock ?

 

[D.A.(Tony)Stewart]

As you know load capacitance and impedance will affect the shape of you clock and the sources of most new devices are lower than most cables. i.e.74ALC ~ 25 ohms so in order to manipulate the same shape, you need the same impedance ratios. Since you have no specs, all I can suggest at the moment is to use different impedances to drive the fan out inside and the external load so they have the same prop. delay if they have the same threshold. e.g. use Rs internal series R ~ >=25ohms and external use Rs = 50 ohms to match cable then use pull-up/down or active termination R to optimize the external clock to the threshold.

 

[fragnen]

What is being heard that there are standard ways to do that. Can anyone suggest some standard way?

 

[dick_freebird]

If you really want synchrony then maybe what you need is to send
the clock off chip, and run both SoCs' blk_A from pin inputs from the
same source. If you want good shape at high frequency then controlled
impedance differential is the only way - LVDS ought to be commonly
available, if you need faster then you shouldn't be thinking any of it's
"digital".

 

[fragnen]

---

If you really want synchrony then maybe what you need is to send
the clock off chip, and run both SoCs' blk_A from pin inputs from the
same source.

Do you want to mean that to use an external PLL and send the same clock to the Clk pin of the SOC and the clk pin of blk_A?

--- Updated Oct 19, 2023 ---

if you need faster then you shouldn't be thinking any of it's
"digital".

What do you mean by this?

--- Updated Oct 19, 2023 ---

Let the problem be stated more clearly:

There is a SOC named SOC_S and a clock named Clock_S comes as an output of SOC_S and traverses outside the SOC_S to the Clk_A pin of a block named blk_A and blk_A is sitting outside the SOC_S. The Clk_A is the clock input pin of blk_A. The blk_A runs on Clk_A.