I am facing a situation which I don't know how to handle, I am not even 100% sure it is a problem but I think this is one of those most basic layout problems which you don't want to make.
I often like to make my schematics with very unconventional stuff in order to illustrate to my self where the returns go and which components is critically connected to some point and so forth, the following schematic however is made purely for this post and the colours have meaning:
green = ordinary nets in eagle cad.
turquoise = V
DD(the supply that powers the gate drives and logic within CSD95472)
purple = return for V
DD
yellow = V
IN supply(this is the supply that feeds the 40A synchronous buck-converter)
red = return for V
IN
The CSD95472 have two
PGND(I keep calling it PGND as it is called in it's datasheet but that doesn't indicate that there is another GND for other function in this package in this case) pins(one is a ordinary pin and the other is the large heat sink pad) and those two pins should be connected directly to each other. An alternative to the CSD95472 is the CSD95373 which is very similar, in the same package but without some of the pin functions that CSD95472 have, amongst other things the CSD95373 has only one
PGND pin. I think I will go with the CSD95472 even though it is a little higher in cost its extra
PGND pin makes the layout quite a bit easier.
But as the schematic tries to indicate, I have from the very start planned to route the return for the high-current buck-converter with it's very own GND path, but since the CSD
WHATEVER requires a lower V
DD voltage(lower than V
IN in my case) that V
DD is derived from a integrated buck converter, before going further let me tell you what that converter does.
The TPS62135 features a V
SEL pin and two feedback connections(FB and FB
2) FB
2 are connected to GND through a NMOS that is controlled by V
SEL. So while V
SEL isn't activated the feedback voltage divider results in one output voltage which can then be changed by activating V
SEL placing a second FB resistor
lower in parallel with the first altering the feedback.
Which is an idea to be used like this:
The µC MCU is powered by the REG101(which has great PSRR ratings) set to 3,3V, REG101 can operate with very small drop-out voltages(which degrades it's performance) so when the device isn't actively being used the the µC setts the V
SEL pin of TPS62135 so that it outputs a voltage above 3,3V but as close to that value as is safe to use. Then when the device are informed it is to activate and needs to perform analog-to-digital conversions, the µC makes the TPS62135 to increase it's output voltage into 5V which also brings that voltage into the range of what the CSD95472 requires(the CSD... is also controlled by a ENABLE signal) so so that the power loss due to the REG101 LDO is minimized.
Also the TPS62135 have a quite new operating function which makes it to automatically enter some low power mode when the output current is low, which really extends the converters efficiency at low currents.
And now I have gone through it all so the issue is that I want to keep the µC supply as clean as possible as that will also power current sense amplifier(s), maybe a differential amplifier and maybe even a ADC with an internal reference to enhance the resistance measurement compared to the µC's internal ADC.
So then I don't want to pass that 40A return through the ground of the TPS62135, but if I don't do that wouldn't I then create a ground loop?