seeing negative delay value on input pin of a cell in si timing reports

[naribtech]

Hi,

seeing negative delay value on input pin of a cell in si timing reports. How it is possible ?

xxx/xxxxxx/xxxxx191_ (net)

xxx/xxxx/xxxxxxxxxxxxxxx191_/A (hdbfxss1uhd)
0.000 0.032 -0.007 -0.006 & 0.301 f
xxx/xxxxxxxxxx/xxxxxxxxxxxxxxxxxxx_/Z (hdbfxss1uhd)
0.035 0.031 & 0.332 f


Thanks,
Nari.

 

[sam536]

Negative net delays can be seen due to following reasons :

voltage scaling
threshold scaling
crosstalk delay effects

Voltage Scaling

when you use different supply voltages in Signoff and If you do not define a global operating condition, the default operating condition for each library is used.

If the driver has an higher supply voltage than the load, the waveform at the load pin reaches the delay threshold earlier than at the driver pin. This results in a negative net delay.

Threshold Scaling

PT uses the delay and slew thresholds defined in each library. Therefore, the net delay is not necessarily measured between identical thresholds. If the threshold on the load pin is reached earlier than the threshold at the driver pin, the net delay is negative.
To revert back , set the variable lib_thresholds_per_lib to false.


Crosstalk Delay Effects

Crosstalk delay effects are computed per stage.

Crosstalk changes the effective capacitance of the net, and driver cell delay also changes. If the stage delta delay is larger than the net delay, a negative net delay is reported. The stage delay should be greater zero.


Regards,
Sam