Thanks for farmerwang and IanP's kindly reply.
We do implement remap in our SOC. The flash is remapped to address 0x0 when boot up.
Then the remap is cleared, and SDRAM is initialized. After that, the processor moves code from flash to SDRAM, and executes code from SDRAM later.
To farmerwang, Since I'm not familiar with SDRAM, could you please tell me what does 'MC' stand for, and when should I allocate time for SDRAM device initialization?
To IanP, Do you means the reset IC will give different reset pulse for processor and SDRAM? In our design, there is a reset generation block, which release SDRAM controller's reset signal earlier than processor's in normal operation mode. but in reset-bypass mode, the two resets are de-asserted at the same time, so causes error.