SDF questions and NCSIM question

[tok47]

neg_tchk + example

Recently, I just start to use ENCOUNTER and NCSIM. And now facing some problem wish to get some help.

In the recent timing simulation (we here called it as APR sim), I found some timing violation in my result.

After some debugging activities, I found out that there were some missing TIMINGCHECK information for flops and latches in my sdf file.

In my sdf file, it just shown

(CELL
(CELLTYPE "dffp_1x")
(INSTANCE xxxxxxx/xxxxx/xxxx/xxx
(DELAY
(ABSOLUTE
(IOPATH (posedge CK) Q (0.264::0.768) (0.287::0.853))
(IOPATH (posedge CK) QN (0.290::0.873) (0.271::0.799))
)
)
(TIMINGCHECK
)
)

So, my simulator prompt a error message on ' ) ' and stop loading the rest of the file after the error line.

After I manually remove those error lines. My simulation looks fine for those delay between 1 signal and 1 signal (interconnect).

But, now, I notice another error. The time delay between input and output of certain logic was alway 1ns.


Q: 1. Is this time delay information for logic cell is determine in sdf file?

2. Is this error cause by the sdf file or other standard library?

3. ' 1ns ' seems like a default value from NCSIM. Is it I missed out something in my setting?


Thanks

 

[ljxpjpjljx]

ncverilog neg_tchk

the sdf is matched with your netlist?

 

[santhosh007]

ncverilog pulse_r

Recently, I just start to use ENCOUNTER and NCSIM. And now facing some problem wish to get some help.

In the recent timing simulation (we here called it as APR sim), I found some timing violation in my result.

After some debugging activities, I found out that there were some missing TIMINGCHECK information for flops and latches in my sdf file.

In my sdf file, it just shown

(CELL
(CELLTYPE "dffp_1x")
(INSTANCE xxxxxxx/xxxxx/xxxx/xxx
(DELAY
(ABSOLUTE
(IOPATH (posedge CK) Q (0.264::0.768) (0.287::0.853))
(IOPATH (posedge CK) QN (0.290::0.873) (0.271::0.799))
)
)
(TIMINGCHECK
)
)

So, my simulator prompt a error message on ' ) ' and stop loading the rest of the file after the error line.

After I manually remove those error lines. My simulation looks fine for those delay between 1 signal and 1 signal (interconnect).

But, now, I notice another error. The time delay between input and output of certain logic was alway 1ns.


Q: 1. Is this time delay information for logic cell is determine in sdf file?

2. Is this error cause by the sdf file or other standard library?

3. ' 1ns ' seems like a default value from NCSIM. Is it I missed out something in my setting?


Thanks

it looks like your simulator is not reading the timing values from sdf.

Did you give ncsim ncsim command options like
+ncaccess+r+w

+pulse_r/0 +pulse_e/100 +no_pulse_msg

+neg_tchk

+transport_path_delays

+multisource_int_delays

+maxdelays // max corner

+sdf_verbose

+nowarnTFNPC

 

[tok47]

unit delay in ncsim

I already check my netlist and sdf. Both are cross match.

I am now checking for the NCSIM setting.

Thanks

 

[tok47]

ncsim options maximum simulation time

NCSIM command option is OK.

 

[littlebu]

ets .sdf

hi tok47

maybe you can check "unit delay" option in your NCSIM setting. you have to remove this option.

hope it can give you some help.

littlebu

 

[tok47]

+neg_tchk

Hi littlebu,

Thanks for your input.

I already have that option remove previously.

I am trying to use VCS's sdf file to run in NCSIM with the same setting. It works.

So, I think the error should cause by ENCOUNTER's sdf file. May be I miss out some option when I write the sdf file.

BTW, do you know what is the different between the sdf file that generate by ETS and sdf file that generate by ENCOUNTER?

Thanks

tok47

 

[no_mad]

ncsim with sdf

Hi tok47,

ETS is stands for Encounter Timing System. Thus, what do u mean by the diff between sdf file generated by ETS and Encounter.

Pls clarify.
Thanks

 

[tok47]

sdf delay format example

I was trying to understand the format of these 2 files. I found out that the size of these 2 file has lot different.

Lets say mayb SDF by ETS has timing information for logic A, B, C and D.

But SDF by ENCOUNTER just has timing information for logic A,B and D. This is just an example.

I able to let my simulation works now. There were lesser timing violation complaint in my simulation log file. So, I adding a config file to set timing for the path that complaint timing violation in my log file.