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# sdf back annotation problem with ncverilog. PT spef sdf

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#### weben

##### Newbie level 5
hi,

I back annotated netlist with the sdf file which is generated by Primetime from spef file. But when I was running the post-simulation with ncverilog, I got the messages,

ncelab: *W,SDFRDE: Read error for default code, skipping annotation of tst13.sdf.X.
ncelab: *W,SDFRDE: Read error for default code, skipping annotation of tst13.sdf.X.
ncelab: *W,SDFRDE: Read error for default code, skipping annotation of tst13.sdf.X.

which are the same messages in the thread below.
https://www.edaboard.com/threads/193499/

Refering to the solution, I have tried to delete the .X file and run again. But the messages are still there.

BTW, if I use the sdf file generated by ICC instead, the back annotation can be done successfully. However, I am not going to use this method due to the low accuracy delay information of this sdf file.

Can anyone tell me the possible reasons of why my PT generated sdf file can not be used for back annotation with ncverilog?vv

#### yx.yang

##### Full Member level 4
hi,

I back annotated netlist with the sdf file which is generated by Primetime from spef file. But when I was running the post-simulation with ncverilog, I got the messages,

ncelab: *W,SDFRDE: Read error for default code, skipping annotation of tst13.sdf.X.
ncelab: *W,SDFRDE: Read error for default code, skipping annotation of tst13.sdf.X.
ncelab: *W,SDFRDE: Read error for default code, skipping annotation of tst13.sdf.X.

which are the same messages in the thread below.
https://www.edaboard.com/threads/193499/

Refering to the solution, I have tried to delete the .X file and run again. But the messages are still there.

BTW, if I use the sdf file generated by ICC instead, the back annotation can be done successfully. However, I am not going to use this method due to the low accuracy delay information of this sdf file.

Can anyone tell me the possible reasons of why my PT generated sdf file can not be used for back annotation with ncverilog?vv

Hi, You may use old version of ncverilog and much newer version of PT. You may:
1): Choose to use a little old version of PT.
2): Choose to use newer version of ncverilog
3): Write 2.0 or maybe 1.2/1.1 format of SDF file from PT.

#### weben

##### Newbie level 5
hi, yx.yang.

I rewrote both 2.1 and 1.0 SDF files from an old version PT and ran with the latest version of ncverilog before. But it doesn't work.

thank you anyway.

#### yx.yang

##### Full Member level 4
Hi, I have meet this problem before.
Then I use the Candence P&R tool write out SDF, then back annotate is ok.

PS: Don't think p&R tool maybe not as accurate as PT. You see that P&R tool write out RC files, so you need truch P&R tool sometimes. And even there maybe less than 100ps(just for example) un-accurate in the SDF written out by P&R tool. This may still ok, becase there does exit some points gate sim may not cover, such as:
1): Clock jitter (you can choose to change your PLL model)
2): OCV effict
3): The additional "uncertainty" value you set in PT, expecially for hold time check.

So, trust P&R tool and PT, then gate sim just give your more confidency and check the points can't covered by PT.

Last edited:
weben

### weben

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#### weben

##### Newbie level 5
thanks yx.yang.

I'll use SDF file from PR tool if SDF file from PT is still not OK.

#### otogyg

##### Newbie level 4
hi weben

now i have same problem!

Have you settle this problem.

please help me !

thank you very much.

weben

### weben

Points: 2
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#### weben

##### Newbie level 5
hi weben

now i have same problem!

Have you settle this problem.

please help me !

thank you very much.

Yes we found the reason of this problem. you can change PT's multi-core attribute like this
Code:
set_host_options -max_cores 1
then write sdf.
hope it helps.

bwang0810

### bwang0810

Points: 2
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#### tony_taoyh

##### Full Member level 2
Yes we found the reason of this problem. you can change PT's multi-core attribute like this
Code:
set_host_options -max_cores 1
then write sdf.
hope it helps.

I have same problem as described, with following setup:
a) PT: 2012.12
b) NC: ius10-20.021

#1. I tried "set_host_options -max_cores 1", it does not work.

#2. After trying about 3 hours, I found the solution:
write_sdf -version 3.0 -include [list RECREM] -exclude [list no_condelse] -context Verilog -input_port_nets -output_port_nets $REP_PATH/${TOP_NAME}_pt.sdf

#3. It is compulsory to fix the "ncelab: *W,SDFRDE: Read error for default code, skipping annotation".
One hint is to check the delay of CTS before and after the fixing.

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