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you need to insert scan chain to your design and use ATPG tool to generate pattern. With scan chain inside and the pattern, the ATE tool can find the faulty chips.
People insert scan design (scan chains) in original circuit so that the controllability and observability of the circuit have been improved, i.e. the testability of the circuit has been improved. Besides this benefit, with the insertion of scan chains, the complexity of ATPG has also been reduced since sequential circuit turns into combinational circuit from the viewpoint of ATPG. Normally, people don’t want to put any extra logic into their original design for test purpose only; however it seems that the scan design has been the one of few exceptions which introduce extra overhead to original design and also have been widely accepted by the industry.
forget the 'theory', scan based theory(tedious) has been matured for long, you dont need it unless you want to specialize in testing or test relate tools development. As designer, all you need know is some design rule for test.
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