I am trying to generate scan based test patterns for sequential circuit (iscas s27 for example) for testing only the compinational part for stuck-at faults. I have followed the required steps (providing the scan inserted circuit, .spf files), however the collapsed fault list shows the faults in test_se,test_so, test_si , CK and the clocks and scan enable etc for each flip flops etc in addition to the faults in the combinational logic. Please help!
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