Saving power in FPGA

[shaiko]

My FPGA has 4 banks.
The pins of 3 of the banks are active and communicating only a small portion of the time.

The 4th bank is always communicating and checking the states of its inputs.
Will it be safe to turn of the power of the 3 banks when they're inactive and switch it on when needed ?

 

[aruipksni]

My FPGA has 4 banks.
The pins of 3 of the banks are active and communicating only a small portion of the time.

The 4th bank is always communicating and checking the states of its inputs.
Will it be safe to turn of the power of the 3 banks when they're inactive and switch it on when needed ?

probably not, but depends on the fpga. just look at the fpga's documentations.

 

[star_golden]

Instead of that or in addition to that, you may also want to try clock gating for power reduction. Turn on the clock only when it is necessary by asynchronously sensing the inputs

 

[shaiko]

Turn on the clock only when it is necessary by asynchronously sensing the inputs

I already do that...

 

[TrickyDicky]

Instead of that or in addition to that, you may also want to try clock gating for power reduction. Turn on the clock only when it is necessary by asynchronously sensing the inputs

Clock gating is NOT recommended in an FPGA. you end up using more power as you dont use the clock nets. Its best to use clock enables instead.

 

[shaiko]

I didn't use clock gating but actually caused the clock to shutdown with the OE pin of my oscillator.
TrickyDicky,
What do you think about shutting down the power to the banks when they're inactive ?

 

[barry]

I don't think the I/O banks consume much power themselves, compared to the core (read the data sheet). You could tristate your outputs, or set them all low, and that might minimize current.

 

[shaiko]

You could tristate your outputs, or set them all low, and that might minimize current.

I did that too and it did help...but I'm trying to save every micro-amp.

 

[barry]

If micro amps matter, maybe you shouldn't be using an FPGA.

 

[shaiko]

I agree, but this a legacy project and changing to a uC isn't an option now.
The device at question is a low power Actel FPGA.