Resistor mismatch is depends on a AR (%.um) parameter
σ(ΔR/R) = AR / SQR(W*L)
So, just as MOS transistors, you just have to increase area to improve matching. However, matching parameter AR is given for closely placed devices.
Thus 0.001% is not feasible on integrated resistors (maybe except those trimmed by laser). 0.001% is barely attainable with integrated MIM capacitors.
Added after 8 minutes:
Sorry, my previous mail was reffering to another subject.
The S&H circuits may be directly integrated on the DAC in some charge redistribution SAR ADC.
In fact, the total capacitance of the capacitors array acts as the Sample capacitor during acquisition time. A sole MOS switch connected to VIN is sufficient to sample the signal on the capacitor's array's bottom plate.
During conversion, the charge is redistributed with a dichotomic algorithm so has to obtain the desired output code.
That way, you may suppress a dedicated amplifier for the SH circuitry.