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ADC sample frequency limitation due to I2C speed limits

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Advanced Member level 5
Jan 9, 2012
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Dear friends,

I found numerous nice ADC with high sampling frequencies above 100 MHz,
I need to interface the ADC output to FPGA board that supports I2C protocol with a maximum fsclk of 400 kHz.

I am thinking that the ADC will be slowed due to the I2C as buttle neck and I wander how the I2C will push the data before the next sampling is coming, in the same time sampling frequency is far bigger than I2C frequency.

One possibility I am thinking that I2C will have a stack memory to store the data to be pushed sequentially, if it is true this mean it is not possible to implement real time DSP with series protocols.

I need you help to clear me this concept and thank you very much in advance



High speed ADC and I2C interface contradcit.
400kHz is the usual I2C SCK frequency. But there are faster I2C standards. I think up to 3.4MHz. But I´m not sure.

Back to 400kHz.
The I2C needs some overhead. So I think you can´t transmit more than 10kSample/s via I2C.
I2C simply was not designed for those applications.

I wonder how/where you have seen something around 100MHz in combination with an I2C ADC.
I can only imagine that you talk about a dual slope ADC or a delta-sigma ADC. Both talk about a high sampling rate but the data rate is much lower than the sampling rate.

It´s not unusual to have a 256 times higher sampling rate than data rate on a delta sigma ADC.
There are even 1024 or 2048 ratios.

If you want high speed, then go for parallel interface. Or LVDS interface.
Mind that LVDS is just the physical layer. There are LVDS parallel interfaces and LVDS serial interfaces.

Fast ADC have fast interfaces. I don't believe there's any I2C ADC with higher sampling rate than interface throughput.

Some high speed ADC have auxiliary I2C or SPI interface for control purposes, are you asking about such device?
Dear friends,

Thank you very much for your nice explanation, as I see that you agree with me that "High speed ADC and I2C interface contradict", as Klaus stated.

here is one example of ADC with sampling rate of 125 MSPS, but as Fvm mentioned, might be the I2C is used for the control, not for the data transmitting, I believe it the point where probably I get confused, but it is good to discuss it with you :D

To follow your explanation, I have to go for a parallel interface if I need to work with high-speed ADC.


as far as I can see the shown ADC has no I2C interface at all.

Here is the search filter from Mouser
If you more rely on a distributor search than on the datasheet ... then you should ask Mouser how they come to the conclusion "I2C". I can not answer this.


The interface is SPI not I2C, apparently the website author didn't read the datasheet thoroughly.

Within the scope of this thread, the difference isn't important I think, the ADC has a slow auxiliary interface for configuration purposes, it can e.g. activate a test pattern on the LVDS outputs, rather useful when you setup the interface. I believe to have seen I2C configuration interface on a different ADC, but don't remember what it was.

Thank you friends for your help and nice discussion,

Yes indeed I have been misled by the Mouser filter, the actual data sheet is different. As Fvm said the difference is not that big, althaugh SPI is much faster than I2C but can not save the speed of 125 MSPS in addition to the high bit resolution which makes it more difficult to push the data fast. So I will follow your suggesion and look only for a parallel interface for high-speed data throughput at high sampling rate beyond the capability of the serial protocols. Also the high speed LVDS protocol can be still considered for this purpose.
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the math is quite simple: (I guess you have done this before)

125M/Samples/s times 4 channels times 16 bit = 8000 Mbits/s or 8GBits/s
(16 bits because the serial interfaces usually go with 8 bits, 16 bits...)

* I2C standard specifies the speed.
* SPI does not specify a speed.

While on a I2C bus the slowest member decides the max. clock speed...
... on SPI you may choose a different speed for each partner. Fast spped for fast partners, slow spped for slow partners.

SPI also does not define the voltage levels and driver timing, thus you may use an LVDS interface and run high speed SPI signals on them.

the math is quite simple: (I guess you have done this before)

125M/Samples/s times 4 channels times 16 bit = 8000 Mbits/s or 8GBits/s
(16 bits because the serial interfaces usually go with 8 bits, 16 bits...)

Thank you very much Klaus, yes I have done before but with this calculation:

sampling frequency X resolution (number of bits) X number of channels X number of overhead data bits.

The overhead data bits represent the addressing and acknowledgement data.

Anyway and considering your calculation of 8 GBits/s, clearly and mathematically prove the demand of fast parallel or LVDS as you suggested before.

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