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Sample and Hold Circuit.

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Syukri

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miller capacitance based sample hold

I'm using Miller capacitance sample and hold cirucit.
For an 8-bit resolution my sample circuit must be able to detect and hold at least 12mV.

Right now I'm only able to make the resolution to 0.2V @ 200mV.

Can I get ant suggestion of how can i achive my targeted resolution.

Thanks in Advance.

Best Regards

Syukri
 

sixth

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sample and hold circuit

Syukri said:
I'm using Miller capacitance sample and hold cirucit.
For an 8-bit resolution my sample circuit must be able to detect and hold at least 12mV.

Right now I'm only able to make the resolution to 0.2V @ 200mV.

Can I get ant suggestion of how can i achive my targeted resolution.

Thanks in Advance.

Best Regards

Syukri
Hi, Syukri
Maybe you should post your schematic and the simulation waveform, which will make the problem more clearly.
For sample and hold circuits
1. The slew rate and the banwidth of the opamp (if you do have a opamp in your circuit) should be large enough to meet the settling requirement.
2. The bandwidth formed by "switch on" resistor and sampling capacitor should be large enough to keep the voltage on the capacitor to track the input voltage
3. The parisitic capacitor of the switch should be small enough comparing with the sampling capacitor to reduce the clock feedthrough.

sixth
 

    Syukri

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Syukri

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sample hold circuit with inverter

this is the schematic takan from journal of ieee

A Compact High-Speed Miller-Capacitance-Based Sample-and-Hold Circuit

Ming-Jer Chen, Yen-Bin Gu, Jen-Yin Huang, Wei-Chen Shen, Terry Wu, and Po-Chin Hsu
 

yeewong_su

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sample and hold circuits

You should use the normal sample hold schematic
 

sixth

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sample hold schematic

Syukri said:
this is the schematic takan from journal of ieee

A Compact High-Speed Miller-Capacitance-Based Sample-and-Hold Circuit

Ming-Jer Chen, Yen-Bin Gu, Jen-Yin Huang, Wei-Chen Shen, Terry Wu, and Po-Chin Hsu
Hi, Syukri

The critical part of this kind of sample and hold circuits is the opamp, namely, the inverter formed by M3 and M4. Does it still has enough gain at hold phase? I mean the operating point maybe change. Once the the gain of the inverter decrease, the effect of charge injection and clock feedthruogh will increase drasticly. You can insert a resistor between the input node and the output node of the inverter to stable the operating point.

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Karthikeya

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hi
try replacing the inverter with an opamp having good gain and common-mode range. Higher the gain higher will the cap during holding phase hence lesser droop.

regards
 

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