run time reconfiguration

[nikhilna007]

how can we perform run-time reconfiguration in fpga's?

 

[permute]

This is the partial-reconfiguration feature. The exact build flow is based on the FPGA and vendor. The vendor should have the most up to date information on what features are supported and which ones are not.

 

[nikhilna007]

This is the partial-reconfiguration feature. The exact build flow is based on the FPGA and vendor. The vendor should have the most up to date information on what features are supported and which ones are not.

which are the xilinx and altera fpga that support runtime recconfiguration.

 

[shahulakthar]

Altera devices:

Stratix® V, Arria V and Cyclone V devices offer support for partial and dynamic reconfiguration

Xilinx devices:

Supports Virtex-4, Virtex-5, Virtex-6, Virtex-7, Kintex-7, Artix-7 FPGA families and the Zynq™-7000

 

[nikhilna007]

Altera devices:

Stratix® V, Arria V and Cyclone V devices offer support for partial and dynamic reconfiguration

Xilinx devices:

Supports Virtex-4, Virtex-5, Virtex-6, Virtex-7, Kintex-7, Artix-7 FPGA families and the Zynq™-7000

thank you sir.

can you provide me some pdf to study about how to perform (steps for) some simple run time reconfiguration examples in these fpgs...

 

[shahulakthar]

check this link for more info

https://www.xilinx.com/tools/partial-reconfiguration

https://www.altera.com/literature/wp/wp-01137-stxv-dynamic-partial-reconfig.pdf










you can find FPGA Kit and learning source at **broken link removed**

 

[nikhilna007]

thank you

expecting more support from all....










you can find FPGA Kit and learning source at **broken link removed**[/QUOTE]