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Rule for bond pad design (removing metal pads)

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Mar 21, 2003
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bond pad design rule

We use TSMC 0.18micron 6 Metal 1 Poly (1.8V/3.3V) technology.We currently use bond pads with a metal pads defined on all 6 metal layers under the passivation bond pad opening. These is a number of vias linking these metal pads together.
The idea is to remove the metal pads from layers 1,2,3 or even from layers 1-5,i.e. to leave the top metal pads only.
We need it to reduce bond pad capacitance.

Can somebody advise on feasibility of this approach from die manufacturing and flip chip assembly point of view?

You should follow the TSMC rules from their DR Document and Bond Rules from your
packaging vendor. I do not think they will allow it.

There is no direct requirement for full stackup of "dummy" pads underneath the final exposed bond pad in TSMC flip-chip design rules. On the other hand the TSMC rules for wire bonding contain the detailed description of such stackup. Also I think this is very similar to a conventional wafer-level re-distribution where bump pad is the only one metal layer with no metal pad stackup below.
However I am not quite sure that this is acceptable for solder bumping and gold SBB both.


As i know, if your chip goes for flip-chip bonding. The bond pad can be reduced as you mentioned. But since your purpose is to reduce the bond pad capacitance, this method will not give your enough reduction. The majority of bonding pad cap comes from the ESD protection device. The better solution is to use low-cap pad design. As i know, as low as 1pF input cap is achieved via TSMC 0.35u process.

Hop it helps : )

Hi sunjimmy,

You are right, it's a problem as well. We have designed our own ESD strurture with reduced capacity of about 0.7pF.

If you want get low cap input pad you can do follow
1. reduce pad size
2. add pad to substrate gap ( just use top mental )
3. ESD protect add clamp circuit ( use clamp circuit reduce the pad cap )
don't use to big mos protect
This my some experience for share


Re: bond pad design rule

have anyone know

circuit under IO_PAD bonding pad ... who about Pad pilling problem ??

Re: bond pad design rule


I problem is PAD peeling issue .. on TSMC .18um

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