RTL work in a test chip

[vlsimember]

How does a test chip team require RTL designers? What do the RTL designers do in a test chip team? Please elaborate.

How does the work of a SOC RTL designer differs from the work of a RTL designer for test chip?

I saw one post in edaboard by mr_vasanth on test chip. But I am looking for some more about test chip.

Regards

 

[anilineda]

How does a test chip team require RTL designers? What do the RTL designers do in a test chip team? Please elaborate.

How does the work of a SOC RTL designer differs from the work of a RTL designer for test chip?

I saw one post in edaboard by mr_vasanth on test chip. But I am looking for some more about test chip.

Regards

In my case, I am an RTL engineer with a exp of 1.8 years. Lets take my case of building a ASIP processor, the customer comes with an idea of implementing an algortihm. we simply understands the math behind the algorithm and will code mathematical instructions needed for that algorithm and if it works fine then it will become the part of the processor Instruction set. And if integrate this IP with some other peripherals like DDR , pCIe, memory and some xyz IP from other vendors, it becomes an SoC. Soc is simply bringing required IP's together via a bus architecture as per requirement. A thorough understanding of verilog, vhdl and able to visualize the behavior and grasping the way our code synthesizes is a skill set every RTL guy should have. This what exactly I'm on.

 

[ThisIsNotSam]

In my case, I am an RTL engineer with a exp of 1.8 years. Lets take my case of building a ASIP processor, the customer comes with an idea of implementing an algortihm. we simply understands the math behind the algorithm and will code mathematical instructions needed for that algorithm and if it works fine then it will become the part of the processor Instruction set. And if integrate this IP with some other peripherals like DDR , pCIe, memory and some xyz IP from other vendors, it becomes an SoC. Soc is simply bringing required IP's together via a bus architecture as per requirement. A thorough understanding of verilog, vhdl and able to visualize the behavior and grasping the way our code synthesizes is a skill set every RTL guy should have. This what exactly I'm on.

this has nothing to do with test. this is RTL writing for sheer functionality.

OP: test is more complex than it used to be. back in the day, you would have a scan chain and that was that, maybe tens of lines of verilog were needed, tops. now you have all these protocols and wrappers. you have IPs in your SoC that are actually test IPs. someone has to design and integrate all of them. this is typically done by an RTL engineer that specialised in test aspects of ASICs.

 

[vlsimember]

Anilineda

Do you work in testchip division? Which country do you work in? May I know which company fo you work in?

Is the experience gain by a RTL Designer working in a test chip team is less, equal or more valuable than the experience gained by a RTL Designer working in a RTL Design team for a SOC or IP ?