Hey all I am looking for the RTL for a pipelined processor which can be synthesized using the Synopsys DC compiler(ASIC synthesizable) any suggestions from anyone as to where can I get these from?
Why do you say pipelined processor? I've never run across an asynchronous processor design.
Try the opencores OpenRisc 1200 it's referred to as a hyper-pipelined RISC processor. I won't vouch for the quality of the code, I've never used a processor off of opencores before.
Just remember the old adage "You get what you pay for" i.e. if you pay nothing don't expect much. ;-)