RTL Encounter VS Design Compiler

[mark_yeh]

the AE from Cadence told me that the design synthesized by their synthesis tool RTL Encounter(RC) is much smaller than by DC(2004.06), and saves much run time. but i am not sure. did anybody here compare the two tools with your own design ?

 

[z81203]

hi, what is rtl encounter? get2chip or buildgates? someone said get2chip is good, but i think dc is still get most support by vendor.

 

[wadaye]

hi, what is rtl encounter? get2chip or buildgates? someone said get2chip is good, but i think dc is still get most support by vendor.

Hi z81203,

Rtl Compiler is the synthesis tool from get2chip, now this tools is belong to

Cadence.

 

[CatKing]

it's true, the same case as synplify vs fpga compiler, but, the dc is the industrial standard now, it's the only problem to replace it with other asic synthesis tools.

 

[AlexWan]

I think RTL Complier is very powerful. It also includes the Physical Complier's function of Synopsys.
But it is very expensive. Certainly, DC is the familiar tool for most designer.

 

[soccer]

Synopsys is accomplished in synthesis tech in EDA industry, i think DC is better than ...

 

[beta1]

the AE from Cadence told me that the design synthesized by their synthesis tool RTL Encounter(RC) is much smaller than by DC(2004.06), and saves much run time. but i am not sure. did anybody here compare the two tools with your own design ?

he lied !

 

[NATHANHSIEH]

SORRY~YOU SAY RTL Encounter(RC) , CAN YOU TELL ME THE "RC" IS CADENCE
DESIGN TOOLS FOR COMPILER??
REPUDETLY DC USEFUL THEN CADENCE'S COMPILER....

 

[niuniu]

it should be RTL Compiler (which integerated in SOC encounter product).

RC has some good feature, but it is still young and need some time to be validated.

DC/MC/PC is still the first selection.

 

[quake]

The results from SNUG are also confusing, it not easy to make clear which is better, but it seems that get2chip's product works well, at least i know that there are some drawbacks with DC

 

[sunlei]

RTL Compiler has the graphics using?

 

[haosg]

However, with DW and data-path optimization, DC can process more complex design and get better
results than RC.
But for non-accurate wire-load model, the result will get worsen after place.
DC + PC + Astro is most powerful flow.
Thus need run DC with new configuration with old flow.