I dont have the original rtl. Besides, I just want to convert from synthesized netlist. There is a procedure for doing this. I followed it and struck here whule converting scan latch into an generic one.
Thanks.
In this case, additional or manual script can help. Look like 2 technology libs are not 100% same.
You can try genus/rtl compiler if you have access to that tool. read in the netlist using both libs, then set_dont_use on all cells of lib A. finally run synthesize, optimize, etc.
I dont have the original rtl. Besides, I just want to convert from synthesized netlist.
:shock:
Why!?
Did someone forget to put the RTL into source control (or perhaps doesn't believe in using it)?
Haha, right. You are so naive
Obviously OP payed for a softcore that was meant for a certain tech. Now OP wants to use that again in a different tech and save a few bucks. Amiright?
I think I am. Someone call the cops!
Haha, right. You are so naive
Obviously OP payed for a softcore that was meant for a certain tech. Now OP wants to use that again in a different tech and save a few bucks. Amiright?
I think I am. Someone call the cops!
Did the tool leave any message about that point ?
I think you need to understand the issue clearly before going through.
Let ask the tool vendor if you are not sure about meaning of that Error/Warning.
There is a trick that you can change only that clock gating cell into new technology lib cell manually.Hi...
I found a clue. Actually It is an integrated clock gating cell not scan latch. And I found some related commands. But yet to try. Anyway got another way to go. if you know anything about this integrated gating cell concept, please share with me. I will try and post the results.. soon.. thanks for the response.
Thanks.
There is a trick that you can change only that clock gating cell into new technology lib cell manually.
It is not a automatic method but it work as the worst case.
The clock gating RTL is not so complicated. You can replace the existing clock gating cell by the equivalent RTL.Hi yeah, we can do that..
But unfortunately my new lib has no exact equivalent of that cell. I need to combine some cells to get the desired operation. I am rying another way.. Deleting the clock gating cells from the synthesized netlist .. so that RC replaces those instances with MUxex then i am going to convert it into generic netlist and then map into new library.. I dont know the success rate .. I will share you if it works as I expected.
Thanks.
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