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RTL compiler Technology Mapping

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kenambo

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Hi All,

I am converting an Already synthesized RTL design from one technology to another technology. While doing this, The old synthesized netlist has a scan latch which has an selection input. The problem is, while converting to generic logic that scan latch is not converted to a generic logic.

For scan flops, we can use
"set_attribute unmap_scan_flops true" But for latches how to get corrct generic logic for the above...

Please explain if you have any other way to do this.

Thanks.
 

slutarius

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I am curious how to you did the conversion.
You have gate level design with technology A.

This is what I did to make a design with technology B.

1/ Set link_library is technology A libs.
2/ Set target_library is technology B libs.
3/ Read the design A -> Link design A
4/ Compile
5/ Write out the design B which will have technology B cells.

Of course, you can resynthesize the RTL with target_library B.
 

kenambo

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I dont have the original rtl. Besides, I just want to convert from synthesized netlist. There is a procedure for doing this. I followed it and struck here whule converting scan latch into an generic one.

Thanks.
 

ThisIsNotSam

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I dont have the original rtl. Besides, I just want to convert from synthesized netlist. There is a procedure for doing this. I followed it and struck here whule converting scan latch into an generic one.

Thanks.

You can try genus/rtl compiler if you have access to that tool. read in the netlist using both libs, then set_dont_use on all cells of lib A. finally run synthesize, optimize, etc.
 

slutarius

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In this case, additional or manual script can help. Look like 2 technology libs are not 100% same.
 

kenambo

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In this case, additional or manual script can help. Look like 2 technology libs are not 100% same.

Hi,
yeah, maybe. But the problem is. even before I introduce the target library, It occurs.. Because it is occuring at generic logic conversion stage. So, when it tried to convert a logic to generic.. It doesn't need another library right?

I think, RTL compiler can't convert every synthesized logic to generic logic. Not sure.... I think so....

But I know there must be some way of overcoming it. I am analysing this... But haven't found any info yet..

If you know anything, please share.. thanks for your interest...

- - - Updated - - -

You can try genus/rtl compiler if you have access to that tool. read in the netlist using both libs, then set_dont_use on all cells of lib A. finally run synthesize, optimize, etc.

Hi.. yeah The procedure is in RTL compiler also.. same steps as you mentioned .. it exists in RTL compiler also...

Thanks
 

ThisIsNotSam

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Is it possible that the scan latches were added manually to the netlist after synthesis? Just a guess. Asking rtl compiler to revert something it didn't add in the first place could be unfeasible.

If you have the same scan latch in the new library (same polarity, inputs, etc), you could just use a simple find&replace for that cell name. then let RTL compiler optimise the rest of the circuit around it. it should work just fine.
 

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I dont have the original rtl. Besides, I just want to convert from synthesized netlist.

:shock:

Why!?

Did someone forget to put the RTL into source control (or perhaps doesn't believe in using it)?
 

ThisIsNotSam

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:shock:

Why!?

Did someone forget to put the RTL into source control (or perhaps doesn't believe in using it)?

Haha, right. You are so naive :)
Obviously OP payed for a softcore that was meant for a certain tech. Now OP wants to use that again in a different tech and save a few bucks. Amiright?
I think I am. Someone call the cops!
 

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Haha, right. You are so naive :)
Obviously OP payed for a softcore that was meant for a certain tech. Now OP wants to use that again in a different tech and save a few bucks. Amiright?
I think I am. Someone call the cops!

More like I don't do stuff like that, so that wasn't my first thought on the subject...Now that you pointed it out, I think we should stop helping them.

Ethics in engineering is dead. I guess I am one of the few remaining practitioners of it. :cry:
 

kenambo

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Haha, right. You are so naive :)
Obviously OP payed for a softcore that was meant for a certain tech. Now OP wants to use that again in a different tech and save a few bucks. Amiright?
I think I am. Someone call the cops!

Hi guys..

It is not about bucks.. it is about knowledge. Besides, I don't belong to digital. I just tried if it works.. and I m using free pdk and tutorials provided by cadence. It is my passion to understand the concepts of synthesis and place and route. If you guys know the way, help me.. or just leave the way.. I will search and find it by myself.

Thanks
 

slutarius

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Did the tool leave any message about that point ?
I think you need to understand the issue clearly before going through.
Let ask the tool vendor if you are not sure about meaning of that Error/Warning.
 

kenambo

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Did the tool leave any message about that point ?
I think you need to understand the issue clearly before going through.
Let ask the tool vendor if you are not sure about meaning of that Error/Warning.

Hi...
I found a clue. Actually It is an integrated clock gating cell not scan latch. And I found some related commands. But yet to try. Anyway got another way to go. if you know anything about this integrated gating cell concept, please share with me. I will try and post the results.. soon.. thanks for the response.

Thanks.
 

slutarius

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Hi...
I found a clue. Actually It is an integrated clock gating cell not scan latch. And I found some related commands. But yet to try. Anyway got another way to go. if you know anything about this integrated gating cell concept, please share with me. I will try and post the results.. soon.. thanks for the response.

Thanks.
There is a trick that you can change only that clock gating cell into new technology lib cell manually.
It is not a automatic method but it work as the worst case.
 

kenambo

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There is a trick that you can change only that clock gating cell into new technology lib cell manually.
It is not a automatic method but it work as the worst case.

Hi yeah, we can do that..

But unfortunately my new lib has no exact equivalent of that cell. I need to combine some cells to get the desired operation. I am rying another way.. Deleting the clock gating cells from the synthesized netlist .. so that RC replaces those instances with MUxex then i am going to convert it into generic netlist and then map into new library.. I dont know the success rate .. I will share you if it works as I expected.

Thanks.
 

slutarius

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Hi yeah, we can do that..

But unfortunately my new lib has no exact equivalent of that cell. I need to combine some cells to get the desired operation. I am rying another way.. Deleting the clock gating cells from the synthesized netlist .. so that RC replaces those instances with MUxex then i am going to convert it into generic netlist and then map into new library.. I dont know the success rate .. I will share you if it works as I expected.

Thanks.
The clock gating RTL is not so complicated. You can replace the existing clock gating cell by the equivalent RTL.
Then, the tool will find necessary clock gating in new technology libs for that RTL.
 

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