RSA implementation - help needed

[efundas]

RSA implementation

I have to implement RSA into an FPGA, for which I require 1024x1204 bit multiplier. the computation time of RSA is 1msec, so I have to increase the hardware to do the multiplications faster but the hardware becomes so huge it does not fit into FPGA. Can anyone help me out.

Y=(E power X) mod P
where, E,X and Y are of size 1024 bits and P is of size 192 bits.

 

[Ace-X]

At least, you can decrease the size of multiplier to 192x192 due to simple rule: (A x B) mod C = ((A mod C) * (B mod C)) mod C.

More tips you can find in Chap. 14 of Handbook of Applied Cryptography:
http://www.cacr.math.uwaterloo.ca/hac/about/chap14.pdf

Ace-X.

 

[Rus]

You may split complex block of the FPGA to small blocks that can compute value in more cycles

 

[destri]

RSA implementation

I'm new member in forum,
How to encrypt file database (paradox) use RSA algorithm and what test scenario that i can do. Anybody can help me?Please..

Added after 2 minutes:

If you have URL RSA. I hope you reply to this forum.thanx you very much