RS232 vhd controller

[JoseL]

hello everybody,

I’m trying to understand how is working the rs232 controller, and I thing I have understood nearly everything, the only thing I can’t understand properly is how calculate the oversampling value to get the data, I mean the baud rate.
I’m working with the digilent’s code RS232RefComp.vhd (https://github.com/ibm2030/IBM2030/blob/master/RS232RefComp.vhd) , at the line 76 is where the sampling rate is calculated, I copy/paste that line:

constant baudDivide : std_logic_vector(7 downto 0) := "10100011"; --Baud Rate dividor, set now for a rate of 9600. Found by dividing 50MHz by 9600 and 16.

When I do the same operation (50000000/9600)/16 it gives me = 325.5 which is aprox. the double than the one is at the code ("10100011" = 163) if I divide per 32 instead 16 the operations match with of the code.

What I’m doing wrong? What’s I missing?

Thank you very much in advance.
Regards.

 

[axcdd]

baudDivide is used to generate not CLK signal. So Actural TCLK frequency is 2* that name as u calculated.
Anyway i discourage learning from that code. Gated clocks, state machines with wrong sensivity list etc.... there are much easier UART driver codes posted on net
like this one http://www.bealto.com/fpga-uart_io.html

 

[ads-ee]

Take a look at the clock generation it is probably toggling based on the baud rate.

Regards

 

[JoseL]

Thank you very much for you help and soon reply, I will have a look to the link.
Thanks again.
Regards.

 

[mrflibble]

My favorite example for rs232:

https://www.fpga4fun.com/SerialInterface.html

The code used in that article is verilog, but a lot of useful hints in there that you can use directly in your vhdl design.