ring oscillator - LVS and post -layout simulation

[kaatml]

Hello,

I have designed a ring oscillator using ams 0.35 tech. I added pads using IOLIBV5_4M library .The schematic simulation works only with net sets.
I have completed the layout with padframe and try to run lvs but i get errors with the pads . The errors are about devices mistmach - Schematic device pin -gndr5r! Device net -gnd! .In Layout - Device pin gnd5r! Device net gndr5r! . I have this problem with every power global supply lines - vdd5r! vdd5o!.....
The schematic simulation doesn't work without net sets but I can validate LVS but after post layout simulation using the extracted circuit, my circuit wont oscillate ! I use Assura , virtuoso .13.
Does anyone have any idea how to pass LVS and post layout simulation with pads ?

 

[erikl]

my circuit wont oscillate ! I use Assura , virtuoso .13.

I guess your D-FF (DF1) cannot drive the connection to the pad and its buffer (BU1P) (fan-out problem). Use a buffer in between.


Also check this thread, and perhaps also this one.

 

[kaatml]

non i have tied with buffer . It's doesn't work .... the result of LVS :

==========================================================================[PAD]
====== Matched Instances with Bad Net Connections =============================
===============================================================================

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(badcon 1)
Schematic Instance: I139 BU1P_V5
Layout Instance: |I139 BU1P_V5

Pin SchNet : LayNet
--- ------ : ------
gnd5o! gnd! : gnd5r!
vdd3r! vdd! : vdd3r!
vdd5o! vdd! : vdd5o!
vdd5r! vdd! : vdd5r!

 

[erikl]

===[PAD]
====== Matched Instances with Bad Net Connections =============================
= = =(badcon 1)

Schematic Instance: I139 BU1P_V5
Layout Instance: |I139 BU1P_V5

Pin SchNet : LayNet
--- ------ : ------
gnd5o! gnd! : gnd5r!

See this post!