dpaul
Advanced Member level 5
Hi,
I have a situation in which I need to simply route the traffic from one Ethernet port to another Ethernet port. I want to achieve this by connecting the RGMII tx-rx of one port to the RGMII rx-tx of another port in the FPGA. In other words a functioning 1:1 hub (if I am not mistaken) is desired.
Environment- Vivado 2015.4 + AC701 board + Extenstion board= Ethernet FMC (from Opsero.com) having 4 Marvell 88E1510 RGMII capable PHYs with 4 RJ45 sockets and of course an FMC connector.
It is a very simple Verilog code. If the SW2 DIP sw0 from the AC701 board is 1 then then the MUX allow the crossover connection as shown. Else there is no crossover connection. I have also generated the RESETn from the FPGA logic with the specific timmings so as to reset the Marvell PHYs. For me in principle it looks like data transmission should be possible from one port to the other.
When I perform the implementation of the above concept using the bit-stream, I see the PHYs being active (LEDs @ the RJ45 connectors blink). But my PC Eth card is not able to connect to the outside world/the default gateway. It shows Limited Connectivity message (a few minutes after showing not connected).
Is this a valid RGMII connection or am I making a mistake? If not then why can't my PC Eth card connect to my default gateway?
More info can be provided on request.
I have a situation in which I need to simply route the traffic from one Ethernet port to another Ethernet port. I want to achieve this by connecting the RGMII tx-rx of one port to the RGMII rx-tx of another port in the FPGA. In other words a functioning 1:1 hub (if I am not mistaken) is desired.
Environment- Vivado 2015.4 + AC701 board + Extenstion board= Ethernet FMC (from Opsero.com) having 4 Marvell 88E1510 RGMII capable PHYs with 4 RJ45 sockets and of course an FMC connector.
It is a very simple Verilog code. If the SW2 DIP sw0 from the AC701 board is 1 then then the MUX allow the crossover connection as shown. Else there is no crossover connection. I have also generated the RESETn from the FPGA logic with the specific timmings so as to reset the Marvell PHYs. For me in principle it looks like data transmission should be possible from one port to the other.
When I perform the implementation of the above concept using the bit-stream, I see the PHYs being active (LEDs @ the RJ45 connectors blink). But my PC Eth card is not able to connect to the outside world/the default gateway. It shows Limited Connectivity message (a few minutes after showing not connected).
Is this a valid RGMII connection or am I making a mistake? If not then why can't my PC Eth card connect to my default gateway?
More info can be provided on request.