yolco
Member level 2
Hi,
after calculating the trace width for 50 Ohm impedance line, the width is 0.30 mm.
![RF_traces.JPG RF_traces.JPG](https://www.edaboard.com/data/attachments/52/52324-0a99eeb504a19591b343e0034225e576.jpg)
Regards.
after calculating the trace width for 50 Ohm impedance line, the width is 0.30 mm.
![RF_traces.JPG RF_traces.JPG](https://www.edaboard.com/data/attachments/52/52324-0a99eeb504a19591b343e0034225e576.jpg)
- There is no problem at traces but on QFN pins which have a limited spacing, could RF traces have a neck near to SMT pins without affecting too much to RF line impedance? So, RF traces fit in a proper way to avoid any DRC error.
- In case there's no option to reduce the line width in this case, if I maintain the current line width, will the nearest pins (VDD) to RF ones affect to RF signal integrity?
- Does any rule of thumb to route the RF trace on the PCB?
- What is the common clearance between the RF trace and ground plate?
Regards.