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RF power amplifier design advice needed

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guitar_man

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Hello,

I'm designing an RF power amplifier (PA) and have stumbled on a problem. First of all, the PA has 2 stages - 1st stage is A class, 2nd stage - meant to be AB class. Output matching is precisely fixed to the required frequency.
The problem sound like this: I get a maximum amplitude of 400 mV at the gate of the output stage. Don't get me wrong, the input stage does it's work and amplifies the input signal to 2V p2p. But there is a 5-10 ohm stability resistor at the gate of the output stage and I guess that it is the bottleneck. Inter-stage matching is also included so that should not be the case.

Drawing1.jpg

There is also quite a big DC blocking capacitor (100-150 pF) before the stability resistor (at the output of the first stage), but the mentioned 2 V p2p swing is measured at it's output...

As a result, my output stage is not in AB class mode (that's first of all) and the full potential is not achieved. So, is there any way of increasing the voltage swing at the gate? Maybe that's the maximum I can achieve and if I want to increase the output power - just increase the size of the output stage?

I'd appreciate any words of advice on this.
Regards,
Aleksandr.
 

Ow@i$

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Well two things here i would like to tell or know.
1) why using 5 to 10 ohm resistor for stability if your K/Mu factor is more than 1 for let say 2 ohm then use it, point is to use minimum resistance at gate for stability. i suppose you are using ADS for simulations so it can easily be verified there.
2) secondly you said matching is not the issue... your matching network? does it contain "inductor" in Series path of the input signal.. ??

Blocking cap has nothing to do with this attenuation only if it is properly selected.
One thing as far as i know AC input signal has nothing to do to define your Class of operation. it is your "DC Biasing point" that defined the class, the bias voltage for second stage should be lower than biasing value for first stage, if you want to operate the other in AB.
 

PA4TIM

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Could you place a schematic and tell what the frequency and expected output power should be ?

Have you measured the power, because a huge missmatch gives a high voltage but allmost no power.
 

chuckey

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You talk about the gate of the output device, so its a FET. These have a capacitive input impedance without a resistive component, so It should be possible to resonate out this capacitive reactance, and depending on the Q of the tuned circuit at the output of the driver stage , you should actually get more voltage on the gate then you do on the previous collector or drain.
Frank
 

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