Return to zero circuit

[ykishore]

Design a RZ (return to zero )circuit.

 

[KlausST]

Hi,

It seems you don't have a question.

Klaus

 

[ykishore]

Well, let me make it clear

The question is I want to design a NRZ circuit that generates the waveform shown.

One way of doing it is just using delay and a high-pass latch. But I am just curious if there is any other way of doing it.

Thanks

 

[ads-ee]

It could be done with a delay+inverter and an AND gate.

The AND gate delay specifies the delay from the rising edge of clock and the rising edge of pulse_out.
The DLY+INV+AND gate delay specifies the width of the pulse.

behaviorally it would look something like this:
assign #N clock_dly = clock;
assign #M pulse_out = clock & ~clock_dly;

Does that work for you?

 

[KlausST]

Hi,

Your solution sounds somehow analog.

A digital solution is to trigger (set) with the rising edge, then use a counter to reset it.

You need to consider how your circuit should behave when input signal goes low before timeout.



Klaus