Retention registers characterization

[nitin kala]

Hi all,

1. What is the meaning of setup time for SAVE pin ( asynch pin ) of a retention register wrt CP pin.
2. If SAVE pin is active high, then why only fall_constraint is considered for setup_rising ( CP rising edge ) in .LIB file ?

Regards & Thanks,
Nitin Kala
nitin.kalaji@gmail.com

 

[artmalik]

It is basically means the time taken for the data to be stored in the always on latch. But in industry we try to avoid the timing on "save" pin. These are low activity and kind of DC signal for the chip level. The timing constraints can avoided for the save pin and be taken at the chip level.

 

[nitin kala]

Thanks artmalik.

1. Save is an asynchronous pin. So why to measure setup time for an asynch pin ? generally we measure recovery and removal ( although like setup and hold only ). So why the name setup here ?
2. In .lib file, only setup_rising ( CP pin rising ) for fall_constraint ( SAVE pin falling ) is mentioned. It means when SAVE pin deasserts. So how this can cause problem to me? If it is about SAVE pin rising around somewhere CP ( which i doubt as it is asynch ), probably then i can check for setup violations. But how to check when it is falling.
3. So what do you recommend ? should i characterize this or not as per industry requirements and standards ?

Regards,
Nitin

 

[artmalik]

I use the retention flops with ANY timing on the save pin in chips that we tapeout. It is not required, but i think the characterization guys who generated the .libs have been over enthusiastic the data. If you constraint the design properly, when you are trying to save the data, then all the clocks should be at zero state. You should keep enough time for this to happen. So you can use the .lib number ,use the worst case timing information add some padding. then use this number as the difference in the time before all clocks are shut off to the point you activate the save pin