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Advantages of not instantiating DPRAM but to realize by registers
- Thread starter fragnen
- Start date
fragnen
Member level 5
Should we go for register based memory for large memories then? If not, then why?
ThisIsNotSam
Advanced Member level 5
in ASICs, one flip flop can be easily 2-4x the size of an SRAM bit cell. it's a terrible trade-off.
dick_freebird
Advanced Member level 5
One reason could be lack of a suitable dual port RAM
IP block or compiler, at the foundry in their supported
PDK. I work with some pure play foundries which have
low level PDKs (basic FETs, passives) but no in-house
standard cell, I/O or memory libraries.
Trying to gen up your own SRAM and make it able to
provide functional simulation, pass verification might
be too much of a cost & schedule burden, and make
sense to eat the area instead (at least the guts are
good to go, simulation and verification wise?).
IP block or compiler, at the foundry in their supported
PDK. I work with some pure play foundries which have
low level PDKs (basic FETs, passives) but no in-house
standard cell, I/O or memory libraries.
Trying to gen up your own SRAM and make it able to
provide functional simulation, pass verification might
be too much of a cost & schedule burden, and make
sense to eat the area instead (at least the guts are
good to go, simulation and verification wise?).
fragnen
Member level 5
Why is then the small memories are realized by flipflops?
ThisIsNotSam
Advanced Member level 5
it's faster and you can access as many elements as you want at the same time. with RAM, you have one, sometimes two ports. with flops you have N ports, so to say.
fragnen
Member level 5
How the latency and routing delay will be more for RAMs compared to registers?
dick_freebird
Advanced Member level 5
RAM has large physical extent / wireload, to be
driven by the smallest possible devices. Logic
gates tend to be built with higher drive strength
(it's not like you could go lower, than a SRAM
min-W pair, through a min-W access switch).
driven by the smallest possible devices. Logic
gates tend to be built with higher drive strength
(it's not like you could go lower, than a SRAM
min-W pair, through a min-W access switch).
dpaul
Advanced Member level 4
@fragnen ,
Now before I or anyone else answers the above question related to routing, I would like to ask how much do you know routing for ASICs?
Because someone may post an answer, and then you will be back asking multiple questions based on that answer.
You seem to ask a cascade of questions, due to which we are digressing from the original topic. For clarity in this forum we cater to, 1 thread = 1 topic.
Now before I or anyone else answers the above question related to routing, I would like to ask how much do you know routing for ASICs?
Because someone may post an answer, and then you will be back asking multiple questions based on that answer.
fragnen
Member level 5
I do not work in placement and routing. Hence very less idea about routing.
dpaul
Advanced Member level 4
Because the registers (DFFs) are located very close to your logic blocks whereas the RAMs are located at a certain distance. Also the DPRAMs have a wrapper logic around them which introduces some clock cycle latency while accessing DPRAMs.