resource requirement exceeds resource available

[student13]

I got an error while trying to run CORDIC code which said:
(device is spartan 3E XC3S100E)
error1: Pack:2309 - Too many bonded comps of type "IBUF" found to fit this device.
error2: Pack:18 - The design is too large for the given device and package.
Please check the Design Summary section to see which resource requirement for your design exceeds the resources available in the device.

I saw the Design summary: the percentage utilization of "number of bonded IOBs" is 121%, others are below 100%. what does this mean and how can I correct it?

the code is:

module cordic(z0,x0,y0,xn,yn,en);
input signed [15:0]z0,x0,y0;
input en;
output signed [15:0]xn,yn;
reg [15:0]xn,yn;
parameter [3:0]iter=4'd14;
reg signed [15:0]thetai;
reg [3:0]ii=0;
reg [3:0]i;
reg signed [15:0]zi,xi,yi,xtemp,ytemp;
reg di;
reg [15:0]pi=16'b0110010010000111;
reg [15:0]pi2=16'b0011001001000011;

always @(en)
begin
if(z0[15]==0)
begin
if(z0[14:13]>2'd1)
begin
xi=0-y0;
yi=x0;
zi=z0-pi2;
end
else
begin
xi=x0;
yi=y0;
zi=z0;
end
end
else if(z0[15]==1)
begin
if(z0[14:13]>2'd1)
begin
xi=y0;
yi=0-x0;
zi=z0+pi2;
end
else
begin
xi=x0;
yi=y0;
zi=z0;
end
end
xn=0;
yn=0;
for(ii=0;ii<iter;ii=ii+4'd1)
begin
ytemp=(yi>>>ii);
xtemp=(xi>>>ii);
if(zi[15]==0)
begin
xn=xi-ytemp;
yn=yi+xtemp;
zi=zi-thetai[ii];
end
else
begin
xn=xi+ytemp;
yn=yi-xtemp;
zi=zi+thetai[ii];
end
xi=xn;
yi=yn;
end
//xn=xn/An;
//yn=yn/An;
end

endmodule

 

[FvM]

Sounds like you have specified a VQ100 package with 66 user IO pins, but the design needs 81 pins.

You have designed the CORDIC transformation pure combinationally without any clock. This will result in a rather low maximum speed.

 

[student13]

thank you. so if i implement it using clock, how will i come to know of the number of clock cycles needed? and also how will i come to know about maximum freq clock can have? because all the operations have to be done in one clock cycle. please help me.