Understanding IO requirements for MAX10 Intel Altera FPGA

[gary36]

I was trying to compile my design into MAX10 FPGA 144 QFP Package(Device: 10M02). My IO's are 95 (out of 101). Quartus tool while fitting gives the following error messages
Error (176205): Can't place 93 pins with 3.3-V LVCMOS I/O standard because Fitter has only 91 such free pins available for general purpose I/O placement

If I let the quartus to choose the IO voltage levels, it selects 2.5V and device fitting is successful. Can anybody explain the error as I require all the IOs to be 3.3V

 

[FvM]

You should be able to answer the question yourself, if you check which pins don't accept 3.3V VCCIO. I guess, you have fixed configuration voltage to 2.5V which constrains the respective bank.

 

[KlausST]

Hi,

so either use 3.3V as configuration voltage or just add some logic level converters.
.. either for the configuration signals or the couple signals that are on the 2.5V bank.

Klaus

 

[gary36]

Where Do I get this information from?

 

[ads-ee]

Where Do I get this information from?

You get it by reading the documentation for the MAX10 part you are using. The documentation will tell you how many pins support 3.3V and what restrictions there are about where these pins are.

Usually if you have some pins that don't have to be high speed you could just move those to 2.5V I/O through voltage translators.

 

[KlausST]

Hi,

I did an internet search about "MAX10 10M02 bank supply". The same could you do.

On the first page ... every dcoument is very informative. Most reliable documents are from the manufacturer INTEL/ALTERA.

Klaus

 

[gary36]

Hi KlausST

I came up with the link https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/max-10/pcg-01018.pdf
Referring to Page 14, it state that Bank 1 to 8, we can select any IO standards and VCCIO must be pulled to IO standards that we specify. BTW, I am using single supply device

 

[FvM]

I have no problems to set VCCIO of MAX10 for all banks to 3.3V. If it doesn't work for you, there must be an unsuitable configuration setting.

I presume, the problem can be narrowed down if you read the fitter report thoroughly.

 

[gary36]

This error is flagged only when IO's are above 91. Less than this magic value for 144 EQFP device, there are no issues

 

[KlausST]

Hi,

Do a test:

try with 91 pins.
The compiler will then use all pins available for use with 3V3.
Now check which (2) pins it does not use. Tell us. Or check the alternative use of these remaining pins on your own.

Klaus

 

[gary36]

Hi KlausST,
Will try this , but there should be clarity a head of time. I did a quick fit in 324 pin BGA and it compiles without problem

 

[KlausST]

Hi,

I did a quick fit in 324 pin BGA and it compiles without problem

expectable.

Klaus

 

[FvM]

I can use 100 3.3V GPIOs with this options

1 pin has to be reserved as JTAGEN.

Without JTAG pin sharing, dedicated JTAG pins are substracted from available GPIO count

Error (176205): Can't place 100 pins with 3.3-V LVCMOS I/O standard because Fitter has only 97 such free pins available for general purpose I/O placement
Error (176204): Can't place pins due to device constraints

 

[gary36]

Hi FvM
Yes, it works. But I do not understand why JTAG should be used as general purpose IO. I want to use this as dedicated JTAG port. Where do we find the reference. Please clarify

 

[FvM]

You can also use dedicated JTAG port and get 97 available GPIO.