resistor layout problem in LVS part

[arkeint]

when I run LVS it always gives this error in the view output window and the error summary window would not pop out. I dont understand why it says it cant layout top block

<a title="resistorlayoutlvs.png" href="http://obrazki.elektroda.pl/5638238900_1375896050.png"><img src="http://obrazki.elektroda.pl/5638238900_1375896050_thumb.jpg" alt="resistorlayoutlvs.png" /></a>

 

[AdvaRes]

Maybe it is problem of model file are corrupt.

 

[Subhash]

I would guess below of these may be a reason,
1. In the Hercules lvs run, Lib name from where the "TEST" cellView is being called.
2. Also please check your cds.lib whether the techLib is attached to the library or the techLib is present in the cds.lib
3. We can also try by doing "Check-and-Save" for schematic view before running a LVS run