speedman
Newbie level 6
fpga reset
Hi all,
I'm new in FPGA and I bought a stater kit with spartan3.
There are many example to understand fpga but all of this are with external reset connect to the button.
So, my question : If I implement my design (State machine, Micro .....) who reset my HW. Clock is internal or external, but the reset ?
I've read on use of sync reset that is the best choice, but who generate it ?
I don't know....:|
Hi all,
I'm new in FPGA and I bought a stater kit with spartan3.
There are many example to understand fpga but all of this are with external reset connect to the button.
So, my question : If I implement my design (State machine, Micro .....) who reset my HW. Clock is internal or external, but the reset ?
I've read on use of sync reset that is the best choice, but who generate it ?
I don't know....:|