Yes,
actually i wanted to use maneatis delay stage. If I have understood correctly the symetrical load is necessary to lower dynamic jitter; and replica feedback biasing lower static jitter. My circuit (without symetric load) shows a great amount of static jitter, and this is my problem. i designed a delay cell with identical PMOS transistors both the result was the same. The amplifiers duty is to equate voltages at two input nodes, and it does it perfectly. i haven't considered its PSRR. does it have a large effect on jitter?
it seems to me that maneatis method of designing a supply independent delay cell, does not really work. because although it stabilizes min voltage value, the max voltage value(hence the swing) is still dependent on supply voltage, and therefore, amout of delay changes with supply voltage variation.
This is the exact replica. the ratio is one.