Removing latches generated from missing assignment in if statement

[Kathan Shah]

I have written an if else statement in VHDL, wherein one signal is used in if statement and not in else statement, which has resulted into latch. This should not happen. One way to remove this is assign signal values in both cases, which is not possible for my logic. What I am doing is similar to...

if(c>0) then
a='1';
else
b='1';
end if;

Now latches are generated for a and b signals. What are the different ways to avoid latch formation?

I cannot do like

if(c>0) then
a='1';
b='0';----I dont want b to be 0 here
else
b='1';
a='0';----same here
end if;

 

[achaleus]

assign same values as

if(c>0) then
a='1';
b=b;
else
b='1';
a=a;
end if;

if it is in clock it will not generate latches

 

[Kathan Shah]

Thank you for your suggestion.

b=b will cause reading and writing in same clock cycle which will not be possible.

 

[achaleus]

reading done in the same clock but writing will be in the next clock... that doesn't pose any problem

 

[TrickyDicky]

Latches will always be generated when you do not assign a value in all cases outside of a synchronous process, there is no way to avoid it.
Best answer - synchronise all of your code.

 

[K-J]

Thank you for your suggestion.

b=b will cause reading and writing in same clock cycle which will not be possible.

The 'a <= a' and 'b <= b' assignments will do absolutely nothing, you can leave them out and get the same result. The only way to take the original code and get rid of the latches is to put the 'if/then' statement in a clocked process. If you need the logic to be combinatorial then you will need to change your functional requirements (i.e. 'a' and 'b' will have to have a default value)

Kevin Jennings

 

[Kathan Shah]

I tried doing a= a and b=b but still problem was not solved. I dont know what is causing the problem as I have if statement in a case statement.

 

[TrickyDicky]

assigning a = a and b = b inside an unclocked process is exactly a latch. you need to give a and b explicit valies - no memory allowed.

 

[K-J]

I tried doing a= a and b=b but still problem was not solved. I dont know what is causing the problem as I have if statement in a case statement.

TrickyDicky and I already explained what you need to do. Your source code is describing a latch and then you complain when it gives you a latch.

Kevin Jennings

 

[Kathan Shah]

assigning a = a and b = b inside an unclocked process is exactly a latch. you need to give a and b explicit valies - no memory allowed.

I synchronized it and the latching problem was gone! It required a slight change of logic. I was doing a silly mistake. Thank you for the help for making my work synthesizable!:-D