Remove AOI from Synopsys Design Vision

[punj33]

Hi,

I am using Synopsys Design Vision to convert Behavioral logic to structural for my Verilog File. However, I am getting and-or-invert (AOI) gate in structural logic. I don't want AOI but simple and or/nor gates. How do I do that ? I thought I could change something in class.db but couldn't open it.


Please help !!

 

[tariq786]

use set_dont_use command as follows. Use this multiple times if you dont want more than one gates

set_dont_use [format "%s%s" $STDCELL_LIBRARY {/AOI*}]

 

[punj33]

Thanks.
But $STDCELL_LIBRARY is giving me error. There are no such variables.

 

[tariq786]

you have to put the name of the cell according to your library not like i typed