relaxation oscillator with an opamp with a pole

[akbarza]

hi
I before posted the thread :https://www.edaboard.com/threads/why-this-circuit-oscillate.399457/ and the new my question is about it but I do not know that I must post this question in tail of it or I must open a new thread. So I decided to open a new post.

In the pic, if we replace the ideal opamp with a opamp with one pole as Ainf/(1+f/f0), how can we explain this circuit oscillation? what is the effect of f0 frequency on oscillation frequency of ideal opamp namely f_osc=1/(r3*c1*ln3)?
I tried to solve this with replacing opamp with a voltage dependent voltage source as Ainf(v+ -v-) that was serried by an r and c. but I am not sure and I do not know how solve it.
is there any explanation or guide?
in second stage, if Ainf is large but finite, what is result and effect of this assumption?
Is there any suggestion to simulate this circuit with ltspice?
THANKS

 

[FvM]

As you know, the circuit is usually explained as comparator based relaxation oscillator, because the op output is clipped to the rails most of the time. Respectively the effect of limited open loop bandwidth can be better analyzed by considering a finite rise time and propagation delay than by linear parameters.

Of course, the circuit can be simulated with LTspice. It's up to you to select a suitable OP model, either real OP or e.g. the behavioral UniversalOpamp2 model provided by LTspice.

 

[KlausST]

Hi,

Please read this: https://en.wikipedia.org/wiki/Electronic_oscillator

There are oscillators with sinusoidal output signal. Operating as analog circuits with Rs, Cs (maybe L or XTAL) ... phase shift ... and maybe OPAMPs


There are oscillators with square wave output. Oparating as digital circuits. Also with Rs and Cs...but with delay time and threshold levels. They may use COMPARATORs.

Klaus

 

[danadakk]

Not an expert here but the external RC provides a pole, the OpAmp provides
a pole, at least one dominant pole, many two poles, and of course there is phase
inversion thru Opamp.

This circuit clearly non-linear so analysis complicated. Versus linear oscillator
and LaPlace analysis.

By adding phase shift the net of the addition is to have the freq of oscillation
to drop because we achieve the necessary phase shift earlier in freq domain.

OpAmp oscillators can be done at small signal, and large signal where slewing
affects also influence freq of oscillation, it also introduces non linearity which
makes them more difficult to analyze versus small signal and standard LaPlace
anaysis.

I would bet there is a IEEE paper on this very topic that predicts the point at
which the osc will depart small signal behaviour with accompanying analysis.
Unfortunately I am not a member, do not have library access.

https://www.ee.iitb.ac.in/course/~dghosh/expt2notes.pdf

Regards, Dana.

https://www.ti.com/sc/docs/apps/msp/journal/aug2000/aug_07.pdf

 

[D.A.(Tony)Stewart]

This is similar to the CMOS Schmitt Inverter Relaxation Oscillator except you can control the hysteresis thresholds smaller to obtain a higher frequency while the negative feedback integrator biases the output square wave to an average DC voltage while producing partially-exponential triangle wave.

The upside is the thresholds of hysteresis may be controlled by 1% resistors unlike the 1/3 to 2/3 thresholds of Vdd for CMOS which have wide-temperature range tolerances of about 25% but is ridiculously easy to use and cheap. There is a settling time for startup in all cases as Vc drifts from one rail to the centre of the hysteresis affecting the startup duty cycle. There are ways around to reduce this. The other is CMOS gates tend to have more GBW and higher slew rate than Op Amps as there is no internal compensation needed. (Miller integrator).
- Also, due to high input impedance of CMOS, the clock range can be controlled by a pot over a 200:1 range or over 8 f-decades with RC changes.

The downside is BJT Op Amps often have asymmetric dropouts from each supply rail so the duty cycle is not 50% such as Dan's example in this question from -5 to +3.5 with a duty asymmetry error of about 30% or 2x 1.5/10

The better compromise might be a CMOS output Op Amp with <=1% components if frequency tolerance spec was desired to be <= 4%. But then a MEMs or Xtal XO chip for std. frequencies is even easier and more accurate (<< 100 ppm)

- a single Schmitt CMOS Astable simulation (1 of 6)

alternative ways to create positive feedback (hysteresis) Astable CMOS logic oscillators with negative feedback self bias with 2 normal inverters and NAND Schmitt gates.

- in all cases the response of the capacitor integrated square wave is exponential but somewhat linear over 1/3 of the travel, so the voltage change, V across the resistor , R affects the input dV/dt = V/RC as V ramps this slope changes somewhat so a smaller hysteresis is more linear but a larger one is more immune to noise.

 

[crutschow]

The bottom line is that the pole in the opamp's response will basically affect the rise and fall time as well as the saturation delay of the op amp.
The opamp is acting as a comparator but with generally lower response times than a dedicated comparator, so it only operates well at relaxation oscillator frequencies where the slow rise and fall times do not adversely affect the oscillators operation.

This limits can be determined by an LTspice simulation of the circuit with a model of the desired opamp.