This is similar to the CMOS Schmitt Inverter
Relaxation Oscillator except you can control the hysteresis thresholds smaller to obtain a higher frequency while the negative feedback integrator biases the output square wave to an average DC voltage while producing partially-exponential triangle wave.
The
upside is the thresholds of hysteresis may be controlled by 1% resistors unlike the 1/3 to 2/3 thresholds of Vdd for CMOS which have wide-temperature range tolerances of about 25% but is ridiculously easy to use and cheap. There is a settling time for startup in all cases as Vc drifts from one rail to the centre of the hysteresis affecting the startup duty cycle. There are ways around to reduce this. The
other is CMOS gates tend to have more GBW and higher slew rate than Op Amps as there is no internal compensation needed. (Miller integrator).
- Also, due to high input impedance of CMOS, the clock range can be controlled by a pot over a 200:1 range or over 8 f-decades with RC changes.
The
downside is BJT Op Amps often have asymmetric dropouts from each supply rail so the duty cycle is not 50% such as Dan's example in this question from -5 to +3.5 with a duty asymmetry error of about 30% or 2x 1.5/10
The better compromise might be a CMOS output Op Amp with <=1% components if frequency tolerance spec was desired to be <= 4%. But then a MEMs or Xtal XO chip for std. frequencies is even easier and more accurate (<< 100 ppm)
- a single Schmitt CMOS Astable simulation (1 of 6)
alternative ways to create positive feedback (hysteresis) Astable CMOS logic oscillators with negative feedback self bias with 2 normal inverters and NAND Schmitt gates.
- in all cases the response of the capacitor integrated square wave is exponential but somewhat linear over 1/3 of the travel, so the voltage change, V across the resistor , R affects the input dV/dt = V/RC as V ramps this slope changes somewhat so a smaller hysteresis is more linear but a larger one is more immune to noise.