tahirsengine
Member level 3
Hi,
I am doing a project in which I need to use almost 65 registers, each one of 8 bit wide.
Now the problem is, it will consume around 15% of my FPGA distributed fabric (7 series Zynq processor).
These registers will be used for temporary data storage from some sensors.
I am using VHDL for RTL entry.
Is there any method that I can do this without spending that much space on FPGA? Actually overall space that this design is occupying is around 80% and these registers are contributing almost 15%, which I am not liking, as these buffer registers may be increased up to 200 in future expensions. And in that case I will have no other option, as other parts of the design are increasing as well.
Cheers
Tahirs
I am doing a project in which I need to use almost 65 registers, each one of 8 bit wide.
Now the problem is, it will consume around 15% of my FPGA distributed fabric (7 series Zynq processor).
These registers will be used for temporary data storage from some sensors.
I am using VHDL for RTL entry.
Is there any method that I can do this without spending that much space on FPGA? Actually overall space that this design is occupying is around 80% and these registers are contributing almost 15%, which I am not liking, as these buffer registers may be increased up to 200 in future expensions. And in that case I will have no other option, as other parts of the design are increasing as well.
Cheers
Tahirs