registering ADC data on falling clock edge

[sweethomela8]

I'm using a Xilinx spartan FPGA and want to write some VHDL where I can register the output (10 bit) of an ADC. I continuously clock the ADC at 50Mhz and the rest of the FPGA runs on the rising edge of the 50Mhz clock, I want to be able to register the ADC data on the falling edge of the clock to ensure data stability. How can this be done easily?

Should I have some registers clock the data on the falling edge and then have rising edge logic register those registers on the rising edge?

thanks in advance.

 

[rakko]

You can do that or another way I've seem ADC vendors do is to use positive edge flops on the last stage of the ADC but put some delay elements after these last flip flops. This way your output is pushed away from the clock edge and others can use rising edge flops also to capture your data. Another benefit of this method is that your end user will have more than 1/2 clock period of setup margin which is handy in case the your ADC can not be put in the same vicinity as the customer interface.

 

[anoop12]

I would prefer to register data on falling edge of READ ENABLE ( usually active low) signal to ADC from FPGA. you can use a state machine for that.

 

[permute]

What is the exact clocking scheme? it might be best to use a DCM as a zero-delay clock buffer. from there, you can choose to run the system on any phase-shifted clock. This method has the advantage that clock-to-out of the ADC, and input to Clk (of the system clock), and other delays are largely removed. This setup requires the ADC send an output clock to the FPGA.

it still might be useful to look at the DC switching datasheet to see what the setup/hold margins are for your chosen clock scheme.

It may still be worth using a DCM as zero-delay buffer in the system-sync case, as the input to global clock delay can be several nanoseconds.

In the end, the spartan should have IDDR registers. using these, you can select between rising/falling easily.