In my design i used to assign a 3 bit register to 15 bit register........it works well in simulation ......will it be having any synthesizing problem.......or backend problems......Is there any restriction for usage of it.......
The a=b assignment will work fine - no undefined bits. In general, Verilog temporarily widens all terms on the right side of the assignment prior to executing the operation. You declared b as unsigned, so Verilog widens it with twelve zeros.
By the way, those are 16 and 4 bit registers, not 15 and 3 bits.
It's best to show a complete example. Try to avoid "..." missing information.