Register assignment for diff. width

[lakshminarayanan]

In my design i used to assign a 3 bit register to 15 bit register........it works well in simulation ......will it be having any synthesizing problem.......or backend problems......Is there any restriction for usage of it.......

module tt(.....);
reg [15:0] a;
reg [3:0] b;
............
..........
........
a=b;
........
.......
...
endmodule

 

[yln2k2]

Hi ,

I am a verification eng ....
so my answer may not be complete .

1) If you are infering a register , are you going to asing rest of the bits by some other logic ?

if yes it is ok , not synthesis my remove rest of the bust ....
some thing u are using and without asignment then netlist simulation may give 'x' .

please give more info rest of the bits and you are trying to infer a register ? ....


Thanks & Regard
yln

 

[lakshminarayanan]

NO the remaing bits is not assigned for the register..... i am transferring the content of one register of different width to another register......

 

[echo47]

The a=b assignment will work fine - no undefined bits. In general, Verilog temporarily widens all terms on the right side of the assignment prior to executing the operation. You declared b as unsigned, so Verilog widens it with twelve zeros.

By the way, those are 16 and 4 bit registers, not 15 and 3 bits.

It's best to show a complete example. Try to avoid "..." missing information.