Regarding Verilog Simulation

hello guys, i have been trying to simulate pipelined fft 256 point which was directly downloaded from "opencores.org" website, i have synthesized and implemented the design in vivado 2015, im trying to see all the timing wavefrom, im good with vhdl, the design is with verilog, the design is not simulating, the error im getting is


1)[HDL 9-281] Cannot open include file "FFT256_CONFIG.inc".
["C:/Users/SANDEEP/Desktop/pipelined_fft_256/trunk/TB/FFT256_TB.v":58]

2)[HDL 9-870] Macro <FFT256paramnb> is not defined.
["C:/Users/SANDEEP/Desktop/pipelined_fft_256/trunk/TB/FFT256_TB.v":63]

these two files are already included and defined !!!! kindly plz help waiting for the solution

Properties on the file C:/Users/SANDEEP/Desktop/pipelined_fft_256/trunk/TB/FFT256_TB.v
give you permission to access ?



Regards, Dana.

yes

danadakk said:

Properties on the file C:/Users/SANDEEP/Desktop/pipelined_fft_256/trunk/TB/FFT256_TB.v
give you permission to access ?

View attachment 167693

Regards, Dana.

Click to expand...

Above two problems are solved but still my simulation result is not coming...

shailygarg said:

Above two problems are solved but still my simulation result is not coming...

Click to expand...

Then debug the design...

1. You see and X in the simulation window
2. you find the source of the signal in the code
3. you add the inputs that generate that signal to your simulation waveform window
4. you look at which one cause the X.
5. your repeat 2-4 until you find the source of the problem and fix it.

As this is an FFT maybe you haven't run the simulation long enough, did you read any of the documentation for the core?

ads-ee said:

Then debug the design...

1. You see and X in the simulation window
2. you find the source of the signal in the code
3. you add the inputs that generate that signal to your simulation waveform window
4. you look at which one cause the X.
5. your repeat 2-4 until you find the source of the problem and fix it.

--- Updated Feb 22, 2021 ---

As this is an FFT maybe you haven't run the simulation long enough, did you read any of the documentation for the core?

Click to expand...

ok i will try.. Yes i have read

ads-ee said:

Then debug the design...

1. You see and X in the simulation window
2. you find the source of the signal in the code
3. you add the inputs that generate that signal to your simulation waveform window
4. you look at which one cause the X.
5. your repeat 2-4 until you find the source of the problem and fix it.

--- Updated Feb 22, 2021 ---

As this is an FFT maybe you haven't run the simulation long enough, did you read any of the documentation for the core?

Click to expand...

still not working....